Hostname: page-component-cd9895bd7-mkpzs Total loading time: 0 Render date: 2024-12-28T17:39:04.557Z Has data issue: false hasContentIssue false
  • English
  • Français

Three-dimensional integration: An industry perspective

Published online by Cambridge University Press:  10 March 2015

Subramanian S. Iyer
Subramanian S. Iyer*
Affiliation:
Microelectronics Division, IBM Systems and Technology Group, USA; ssiyer@us.ibm.com
Get access

Abstract

The field of electronics packaging is undergoing a significant transition to accommodate the slowing down of lithographically driven semiconductor scaling. Three-dimensional (3D) integration is an important component of this transition and promises to revolutionize the way chips are assembled and interconnected in a subsystem. In this article, we develop the key attributes of 3D integration, the enablers and the challenges that need to be overcome before widespread acceptance by industry. While we are already seeing the proliferation of applications in the memory subsystem, the best is yet to come with the heterogeneous integration of a diverse set of technologies, the mixing of lithographic nodes and an economic argument for its implementation based on overall system function, and cost rather than a narrow component-based analysis. Finally, an extension to monolithic 3D integration promises even further benefits.

Keywords

Packagingeconomicsdeviceselectronic materialjoininglayeredbonding
Type
Research Article
Information
MRS Bulletin , Volume 40 , Issue 3: Materials challenges in 3D IC technology , March 2015 , pp. 225 - 232
Copyright
Copyright © Materials Research Society 2015 

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

Or-Bach, Z., “Intel vs. Intel,” available athttp://www.monolithic3d.com/blog/intel-vs-intel (August 13, 2014).Google Scholar
Iyer, S.S., Proc. IEEE IEDM 33.1 (2012).Google Scholar
Hennessy, J.L., Patterson, D.A., Computer Architecture—A Quantitative Approach (Morgan Kauffman, New York, 1996), p. 374.Google Scholar
Handy, J., Cache Memory Book (Academic Press, San Diego, 1993).Google Scholar
Iyer, S.S., Barth, J.E. Jr., Parries, P.C., Norum, J.P., Rice, J.P., Logan, L.R., Hoyniak, D., IBM J. Res. Dev. 49 (2), 333 (2005).Google Scholar
Le, H.Q., Starke, W.J., Fields, J.S., O’Connell, F.P., Nguyen, D.Q., Ronchetti, B.J., Sauer, W.M., Schwarz, E.M., Vaden, M.T., IBM J. Res. Dev. 51 (6), 639 (2007).CrossRefGoogle Scholar
Iyer, S.S., Freeman, G., Brodsky, C., Chou, A.I., Corliss, D., Jain, S.H., Lustig, N., McGahay, V., Narasimha, S., Norum, J., Nummy, K.A., Parries, P., Sankaran, S., Sheraw, C.D., Varanasi, P.R., Wang, G., Weybright, M.E., Yu, X., Crabbe, E., Agnello, P., IBM J. Res. Dev. 55 (3), 1 (2011).Google Scholar
Craigie, C.J.D., Sheehan, T., Johnson, V.N., Burkett, S.L., Moll, A.J., Knowlton, W.B., J. Vac. Sci. Technol. B 20 (6), 2229 (2002).Google Scholar
Liao, W.S., Chen, H.N., Yen, K.K., Yeh, E.H., Kuo, F.W., Yeh, T.J., Kuo, F., Jou, C.P., Liu, S., Hsueh, F.L., Lin, H.C., Peng, C.N., Wang, M.J., Wu, W.C., Hu, S.P., Chen, M.F., Hou, S.Y., Jeng, S.P., Yu, C.H., Yee, K.C., Yu, D., Proc. IEEE Symp. VLSI Technol. C18–19 (2013).Google Scholar
Miller, L.F., IBM J. Res. Dev. 13, 239 (1969).Google Scholar
Anderson, O.L., Christensen, H., Andreatch, P., J. Appl. Phys. 28, 923 (1959).Google Scholar
Hybrid Memory Cube Consortium, available at http://www.hybridmemorycube.org.Google Scholar
JEDEC, High Bandwidth Memory DRAM, available at http://bit.ly/1gWBE5E.Google Scholar
Van der Plas, G., Limaye, P., Loi, I., Mercha, A., Oprins, H., Torregiani, C., Thijs, S., Linten, D., Stucchi, M., Katti, G., Velenis, D., Cherman, V., Vandevelde, B., Simons, V., De Wolf, I., Labie, R., Perry, D., Bronckers, S., Minas, N., Cupac, M., Ruythooren, W., Van Olmen, J., Phommahaxay, A., de Potter de ten Broeck, M., Opdebeeck, A., Rakowski, M., De Wachter, B., Dehan, M., Nelis, M., Agarwal, R., Pullini, A., Angiolini, F., Benini, L., Dehaene, W., Travaly, Y., Beyne, E., Marchal, P., IEEE J. Solid-State Circuits 46 (1), 293 (2011).CrossRefGoogle Scholar
Totta, A., Sopher, R.P., IBM J. Res. Dev. 13, 226 (1969).CrossRefGoogle Scholar
Semtech, “Semtech and IBM Join Forces to Develop High-Performance Integrated ADC/DSP Platform Using 3D TSV Technology,” available athttp://bit.ly/1niX1vw.Google Scholar
Sukumaran, V., Chen, Q., Fuhan, L., Kumbhat, N., Bandyopadhyay, T., Chan, H., Min, S., Nopper, C., Sundaram, V., Tummala, R., Proc. IEEE Electron. Compon. Technol. Conf. 557 (2010).Google Scholar
Batude, P., Vinet, M., Pouydebasque, A., Le Royer, C., Previtali, B., Tabone, C., Hartmann, J., Sanchez, L., Baud, L., Carron, V., Toffoli, A., Allain, F., Mazzocchi, V., Lafond, D., Deleonibus, S., Faynot, O., Proc. IEEE Int. Symp. Circuits Syst. 2233 (2011).Google Scholar
Tanaka, H., Kido, M., Yahashi, K., Oomura, M., Katsumata, R., Kito, R.M., Fukuzumi, Y., Sato, M., Nagata, Y., Matsuoka, Y., Iwata, Y., Aochi, H., Nitayama, A., Proc. IEEE Symp. on VLSI Technol. 14 (2007).Google Scholar
Patti, R.S., Proc. IEEE 94 (6), 11214 (2006).Google Scholar
Batra, P., LaTulipe, D., Skordas, S., Winstel, K., Kothandaraman, C., Himmel, B., Maier, G., He, B., Gamage, D.W., Golz, J., Lin, W., Vo, T., Priyadarshini, D., Hubbard, A., Cauffman, K., Peethala, B., Barth, J., Kirihata, T., Graves-Abe, T., Robson, N., Iyer, S.S., “Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology,” paper presented at the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Monterey, CA, October 2013.CrossRefGoogle Scholar
Iyer, S.S., Auberton-Herve, A.J., Eds., Silicon Wafer Binding Technology: For VLSI and MEMS Applications (INSPEC, The Institution of Electrical Engineers, London, UK, 2001).Google Scholar
Suntharalingam, V., Berger, R., Burns, J.A., Chen, C.K., Keast, C.L., Knecht, J.M., Lambert, R.D., Newcomb, K.L., O’Mara, D.M., Rathman, D.D., Shaver, D.C., Soares, A.M., Stevenson, C.N., Tyrrell, B.M., Warner, K., Wheeler, B.D., Yost, D.-R.W., Young, D.J., IEEE Int. Solid-State Circuits Conf. Tech. Dig. 48, 356 (2005).Google Scholar