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Vertical interconnects of microbumps in 3D integration

Published online by Cambridge University Press:  10 March 2015

Chih Chen ,
Doug Yu  and
Kuan-Neng Chen
Chih Chen
Affiliation:
Department of Materials Science and Engineering, National Chiao Tung University, Taiwan; chih@mail.nctu.edu.tw
Doug Yu
Affiliation:
Taiwan Semiconductor Manufacturing Company, Taiwan; chyu@tsmc.com
Kuan-Neng Chen
Affiliation:
Department of Electronics Engineering, National Chiao Tung University, Taiwan; knchen@mail.nctu.edu.tw
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Abstract

With the electronics packaging industry shifting increasingly to three-dimensional packaging, microbumps have been adopted as the vertical interconnects between chips. Consequently, solder volumes have decreased dramatically, and the solder thickness has reduced to a range between a few and 10 microns. The solder volume of a microbump is approximately two orders of magnitude smaller than a traditional flip-chip joint. In contrast, the thickness of the under-bump metallization (UBM) remains almost the same as that in flip-chip solder joints. Therefore, many issues concerning materials and reliability of microbumps arise. This article reviews the challenges related to microbump materials for vertical interconnects, including transformation of solder joints into intermetallic (IMC) joints, necking or voiding induced by side wetting/diffusion on the circumference of the UBM, formation of porous Cu3Sn IMCs, early electromigration failures caused by specific orientations of Sn grains, and precipitation of plate-like Ag3Sn IMCs. An alternative way of fabricating vertical interconnects using direct Cu-to-Cu bonding is also discussed.

Keywords

solderingpackagingbondingelectromigrationdiffusion
Type
Research Article
Information
MRS Bulletin , Volume 40 , Issue 3: Materials challenges in 3D IC technology , March 2015 , pp. 257 - 263
Copyright
Copyright © Materials Research Society 2015 

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