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3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces

Published online by Cambridge University Press:  01 February 2011

Jian-Qiang Lu
Affiliation:
luj@rpi.edu, Rensselaer Polytechnic Institute, Department of Electrical, Computer, and Systems Engineering; Center for Integrated Electronics, Troy, New York, United States
J. Jay McMahon
Affiliation:
j.jay.mcmahon@gmail.com, Rensselaer Polytechnic Institute, Department of Electrical, Computer, and Systems Engineering; Center for Integrated Electronics, Troy, New York, United States
Ronald J. Gutmann
Affiliation:
gutmar@rpi.edu, Rensselaer Polytechnic Institute, Department of Electrical, Computer, and Systems Engineering; Center for Integrated Electronics, Troy, New York, United States
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Abstract

Three-dimensional (3D) integration is an emerging technology that vertically stacks and interconnects multiple materials, technologies and functional components to form highly integrated micro/nano-systems. This paper reviews the materials and technologies for three wafer bonding approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces. Similarities and differences in architectural advantages and technology challenges are presented, with recent research advances discussed.

Type
Research Article
Copyright
Copyright © Materials Research Society 2009

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References

REFERENCES

[1] Lu, J.-Q., “3D Hyper-Integration and Packaging Technologies for Micro-Nano-Systems,” Proceedings of The IEEE, Vol. 97, No. 1, January 2009.Google Scholar
[2] Garrou, P., Ramm, P., and Bower, C., editors, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, Wiley-VCN, May 2008.Google Scholar
[3] Lu, J.-Q., Cale, T.S. and Gutmann, R.J., “3D Integration Based upon Dielectric Adhesive Bonding”, in Wafer Level 3-D ICs Process Technology, eds., Tan, C.S., Gutmann, R.J., and Reif, R., pp. 219256, Springer, 2008.Google Scholar
[4] Niklaus, F., Stemme, G., Lu, J.-Q., and Gutmann, R., “Adhesive Wafer Bonding,” Journal of Applied Physics (Applied Physics Review — Focused Review), Vol. 99, Issue 3, pp. 031101–1-28, Feb. 1, 2006.Google Scholar
[5] Lu, J.-Q., Kwon, Y., Kraft, R.P., Gutmann, R.J., McDonald, J.F., and Cale, T.S., “Stacked Chip-to-Chip Interconnections Using Wafer Bonding Technology with Dielectric Bonding Glues,” 2001 IEEE International Interconnect Technology Conference (IITC 2001), pp. 219221, IEEE, June 4-6, 2001.Google Scholar
[6] Lu, J.-Q., Cale, T.S., and Gutmann, R.J., “Wafer-Level Three-Dimensional Hyper-Integration Technology Using Dielectric Adhesive Wafer Bonding,” Materials for Information Technology: Devices, Interconnects and Packaging, eds., Zschech, E., Whelan, C., Mikolajick, T., pp. 386397, Springer-Verlag, August 2005.Google Scholar
[7] Kwon, Y., Seok, J., Lu, J.-Q., Cale, T.S. and Gutmann, R.J., “Critical Adhesion Energy of Benzocyclobutene (BCB)-Bonded Wafers,” Journal of The Electrochemical Society, 153 (4), pp. G347-G352 (2006).Google Scholar
[8] Lu, J.-Q., Lee, K.W., Kwon, Y., Rajagopalan, G., McMahon, J., Altemus, B., Gupta, M., Eisenbraun, E., Xu, B., Jindal, A., Kraft, R.P., McDonald, J.F., Castracane, J., Cale, T.S., Kaloyeros, A., and Gutmann, R.J., “Processing of Inter-Wafer Vertical Interconnects in 3D ICs,” Advanced Metallization Conference in 2002 (AMC 2002), pp. 4551, eds.,Google Scholar
Melnick, B.M., Cale, T.S., Zaima, S., and Ohta, T., MRS Proc. Vol. V18. 2003.Google Scholar
[9] Lu, J.-Q., Jindal, A., Kwon, Y., McMahon, J.J., Rasco, M., Augur, R., Cale, T.S., and Gutmann, R.J., “Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs,” 2003 IEEE International Interconnect Technology Conference (IITC 2003), pp. 7476, June 2003.Google Scholar
[10] Gutmann, R.J., Lu, J.-Q., Pozder, S., Kwon, Y., Menke, D., Jindal, A., Celik, M., Rasco, M., McMahon, J.J., Yu, K., and Cale, T.S., “A Wafer-Level 3D IC Technology Platform,” Advanced Metallization Conference in 2003 (AMC 2003), pp. 1926, 2003.Google Scholar
[11] Pozder, S., Lu, J.-Q., Kwon, Y., Zollner, S., Yu, J., McMahon, J.J., Cale, T.S., Yu, K., and Gutmann, R.J., “BackEnd Compatibility of Bonding and Thinning Processes for a Wafer-Level 3D Interconnect Technology Platform,” IEEE International Interconnect Technology Conference (IITC 2004), pp. 102104, June 2004.Google Scholar
[12] Chen, K.-N., Lee, S.H., Andry, P.S., Tsang, C.K., Topol, A.W., Lin, Y.-M., Lu, J.-Q., Young, A.M., Ieong, M., and Haensch, W., “Structure Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits,” Technical Digest of IEEE International Electron Devices Meeting (2006 IEDM), pp 367370, Dec. 2006.Google Scholar
[13] Chen, K.N., Tsang, C.K., Topol, A.W., Lee, S.H., Furman, B.K., Rath, D.L., Lu, J.-Q., Young, A.M., Purushothaman, S., and Haensch, W., “Improved Manufacturability of Cu Bond Pads and Implementation of Seal Design in 3D Integrated Circuits and Packages”, in 23rd International VLSI Multilevel Interconnection (VMIC) Conference, ed., Wade, T., pp. 195202, IMIC, September 2006.Google Scholar
[14] Chen, K. N., Fan, A., Tan, C. S., and Reif, R., “Microstructure Evolution and Abnormal Grain Growth during Copper Wafer Bonding,” Applied Physics Letters, Vol. 81, No. 20, pp. 37743776, 2002.Google Scholar
[15] Chen, K.N., Tan, C.S., Fan, A. and Reif, R., “Morphology and Bond Strength of Copper Wafer Bonding”, Electrochemical and Solid-State Letters, 7(1), pp G14–G16, 2004.Google Scholar
[16] Morrow, P., Park, C.-M., Ramanathan, S., Kobrinsky, M. J., and Harmes, M., “Three-Dimensional Wafer Stacking Via Cu-Cu Bonding integrated With 65-nm Strained-Si/Low-k CMOS Technology,” IEEE Electron Device Letters, Vol. 27, No. 5, pp. 335337, 2006.Google Scholar
[17] Patti, R., “Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs,” Proceedings of The IEEE, Vol. 94, No. 6, pp. 12141222, 2006.Google Scholar
[18] McMahon, J.J., Lu, J.-Q., and Gutmann, R. J., “Wafer Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers for Via-First 3D Interconnect,” 55th IEEE Electronic Components and Technology Conference (ECTC 2005), pp. 331336, 2005.Google Scholar
[19] Lu, J.-Q., McMahon, J.J., and Gutmann, R.J., “Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers,” 3D Packaging Workshop at IMAPS Device Packaging Conference, Scottsdale, AZ, March 2023, 2006.Google Scholar
[20] McMahon, J. J., Niklaus, F., Kumar, R. J., Yu, J., Lu, J.-Q., and Gutmann, R. J., “CMP Compatibility of Partially Cured Benzocyclobutene (BCB) for a Via-First 3D IC Process”, in Chemical-Mechanical Planarization—Integration, Technology and Reliability, eds., Kumar, A., Lee, J.A., Obeng, Y.S., Vos, I., Johns, E.C., MRS Proceedings Vol. 867, pp. W4.4.16, Spring 2005.Google Scholar
[21] Gutmann, R.J., McMahon, J.J., and Lu, J.-Q., “Damascene Patterned Metal/Adhesive Redistribution Layers,” in Enabling Technologies for 3-D Integration, eds., C.A. Bower, P.E. Garrou, P. Ramm, and K. Takahashi MRS Proceedings Vol. 970, paper #, 0970-Y04-02, 2006.Google Scholar
[22] McMahon, J.J., Chan, E., Lee, S.H., Gutmann, R.J., and Lu, J.-Q., “Bonding Interfaces in Wafer-Level Metal/Adhesive Bonded 3D Integration”, in The 58th Electronic Components and Technology Conference (ECTC 2008), pp. 871878, May 2008.Google Scholar
[23] Guarini, K.W., Topol, A.W., Ieong, M., Yu, R., Shi, L., Newport, M.R., Frank, D.J., Singh, D.V., Cohen, G.M., Nitta, S.V., Boyd, D.C., O'Neil, P.A., Tempest, S.L., Pogge, H.B., Purushothaman, S., and Haensch, W.E., “Electrical Integrity of State-of-the-Art 0.13 mm SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,” Technical Digest of IEEE International Electron Devices Meeting (2002 IEDM), pp. 943945, 2002.Google Scholar
[24] Burns, J.A., Aull, B.F., Chen, C.K., Chen, C.-L., Keast, C.L., Knecht, J.M., Suntharalingam, V., Warner, K., Wyatt, P.W., and Yost, D.-R.W., “A Wafer-Scale 3-D Circuit Integration Technology,” IEEE Trans. Electron Devices, Vol. 53, No. 10, pp. 25072516, October 2006.Google Scholar
[25] Lee, K.W., Nakamura, T., One, T., Yamada, Y., Mizukusa, T., Hasimoto, H., Park, K.T., Kurino, H., and Koyanagi, M., “Three Dimensional Shared Memory Fabricated Using Wafer Stacking Technology,” Technical Digest of IEEE International Electron Devices Meeting (2000 IEDM), pp. 165168, 2000.Google Scholar
[26] Gann, K., “Neo-Stacking Technology,” High Density Interconnect Magazine, Vol. 2, December, 1999.Google Scholar
[27] Knickerbocker, J.U., Andry, P.S., Buchwalter, L P., Colgan, E.G., Cotte, J., Gan, H., Horton, R.R., Sri-Jayantha, S.M., Magerlein, J H., Manzer, D., McVicker, G., Patel, C S., Polastre, R.J., Sprogis, E.S., Tsang, C.K., Webb, B.C., and Wright, S.L., “System-on-Package (SOP) Technology, Characterization and Applications,” 56th IEEE Electronic Components and Technology Conference (ECTC 2006), pp. 415421, 2006.Google Scholar
[28] Wieland, R., Bonfert, D., Klumpp, A., Merkel, R., Nebrich, L., Weber, J., and Ramm, P., “3D Integration of CMOS transistors with ICV-SLID technology,” Microelectronic Engineering, Vol. 82, p. 529–33, 2005.Google Scholar