Hostname: page-component-745bb68f8f-g4j75 Total loading time: 0 Render date: 2025-01-15T00:59:15.977Z Has data issue: false hasContentIssue false
  • English
  • Français

Backside Storage Non-Volatile Memories: Ultra-Thin Silicon Layer on a Complex Thin Film Structure

Published online by Cambridge University Press:  01 February 2011

H. Silva  and
S. Tiwari
H. Silva
Affiliation:
School of Applied and Engineering Physics, Cornell University, Ithaca NY 14853, USA
S. Tiwari
Affiliation:
School of Applied and Engineering Physics, Cornell University, Ithaca NY 14853, USA
Get access

Abstract

Backside storage memories present an alternative to the conventional front-floating gate geometries by storing charge in defects on the back of a thin depleted silicon channel. This paper focuses on the fabrication of these devices using a modified Smart-Cut™ substrate preparation process followed by standard CMOS processing. The substrate is a complex silicon-on-insulator (SOI) substrate where instead of the buried oxide alone a charge trapping multi-layer stack of oxide-nitride-oxide (ONO) is used as the buried insulator. We demonstrate here the operation of these device structures at ultra-short length scales and summarize the characteristics of their operation.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 830: Symposium D – Materials and Processes for Nonvolatile Memories , 2004 , D1.4
Copyright
Copyright © Materials Research Society 2005

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Bruel, M., Aspar, B., Charlet, B., Maleville, C., Poumeyrol, T., Soubie, A., Auberton-Herve, A. J., Lamure, J. M., Barge, T., Metral, F., Trucchi, S., 1995 IEEE Intl. SOI Conf. Proc. (1995).Google Scholar
2. Kumar, A., Tiwari, S., IEEE Trans. on Nanotechnology 1 (4), 247–254 (2002).Google Scholar
3. Lin, X., Chan, M., 2002 IEEE Intl. SOI Conf. Proc. (2002).Google Scholar
4. Silva, H., Tiwari, S., IEEE Trans. on Nanotechnology 3 (2), 264–269 (2004).Google Scholar
5. Ranica, R., Villaret, A., Mazoyer, P., Monfray, S., Chanemougame, D., Masson, P., Dray, C., Waltz, P., Bez, R., Skotnicki, T., 2004 Silicon Nanoelectronics Workshop (2004).Google Scholar
6. Avci, U., Kumar, A., Tiwari, S., 2004 IEEE Intl. SOI Conf. Proc. (2004).Google Scholar