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Characteristics of Lateral Capacitor Based on High-K Materials

Published online by Cambridge University Press:  01 February 2011

Thottam Kalkur  and
Mark Azadpour
Thottam Kalkur
Affiliation:
kalkur@eas.uccs.edu, University of Colorado at Colorado Springs, Department of Electrical and Computer Engineering, 1420, Austin Bluff Parkway, Colorado Springs, 80933-7150, United States
Mark Azadpour
Affiliation:
mazadpour@email.wcu.edu, West Carolina University, Cullowhee, 28723, United States
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Abstract

In order to take advantage of continued interconnect scaling dimensions in very large scale integrated circuit technology, lateral capacitors with BST dielectric have been proposed. The lateral capacitors have been implemented by platinum/titanium metallization patterned by standard photolithographic techniques and ion-milling. The high-K dielectric BST has been deposited by spin-on MOD and radio frequency magnetron sputtering. The capacitance of lateral capacitor was found to increase with increase in thickness of BST and annealing temperature. The negative temperature dependence capacitance above room temperature shows that BST is in para-electric phase.

Keywords

ferroelectricdielectric propertiesPt
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 928: Symposium GG – Current and Future Trends of Functional Oxide Films , 2006 , 0928-GG08-04
Copyright
Copyright © Materials Research Society 2006

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References

1) Kingon, A.I., Streiffer, S.K., Baseri, C. and Sommerfelt, S.R., MRS Bulletin, 21, 7, 46 (1996).Google Scholar
2) Fitsilis, F., Regenery, S., Ehrhart, P., Waser, R., Schienle, F., Scumacher, M. and Juergensen, H., Integrated Ferroelectrics, vol. 38, 211–220 (2001).Google Scholar
3) Chang, W.T., Horwitz, J.S., Carter, A.C., Fond, J.M., Kirchoefer, S.W., Gilmore, C.M. and Christey, D.B., Appl. Phys. Lett., 74, 1033 (1999).Google Scholar
4) Kotecki, D.E., Baneicki, J.D., Shen, H., Liabowitz, R.B., Saenger, K.L., Lian, J.J., Shaw, T.M., Athavale, S.D., Cabral, C. Jr., Duncombe, P.R., Gutsche, M., Kunkel, G., Park, Y.-J., Wang, Y.-Y. and Wise, R., IBM Journal of Research and Development, vol. 43, no. 3, 367 (1999).Google Scholar
5) Baniecki, J. D., Laibowitz, R. B., Shaw, T. M., Saenger, K. L., Duncombe, P. R., Cabral, C., Kotecki, D. E., Shen, H., Lian, J., and Ma, Q. Y., “Effects of Annealing Conditions on Charge Loss Mechanisms in MOCVD Ba0.7Sr0.3TiO3 Thin Film Capacitors,” J. Eur. Ceram. Soc. 19, No. 6-7, 1457 (1999).Google Scholar
6) Uyemura, John P., Chip Design For Submicron VLSI, Thomson publishers, 2006.Google Scholar
7) Lee, Thomas H., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge, 2004.Google Scholar
8) Samavati, H., Hajmiri, A., Shahni, A.R., Nasserbakht, G.N. and Lee, Thomas, IEEE Journal of Solid State Circuits, vol.33, no.12, 1998.Google Scholar
9) Yi, W.C., Kalkur, T.S., Phiofsky, Elliott and Kammerdiner, L., Thin Solid Films, vol. 402, 1–2, 307 (2002).Google Scholar