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Current Status of LSI Micro-fabrication and Future Prospect for 3D System Integration

Published online by Cambridge University Press:  26 February 2011

Kazuya Okamoto
Kazuya Okamoto*
Affiliation:
kokamoto@casi.osaka-u.ac.jp, Osaka University, Center for Advanced Science and Innovation, 2-1, Yamadaoka, Suita, Osaka, 565-0871, Japan
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Abstract

Micro-fabrication technology for LSI devices has been progressing technically over time. However, the scenario of continuing to produce ever-finer feature geometries has a low probability. Resolution capabilities will reach a critical limit due to conventional CMOS performance threshold and chip economy. Therefore, to assure continued performance improvements for future devices, front-end fabricators should consider a new 3 dimensional structure (3D-LSI) using a “Through-Si-Via” process. At the same time, the definition of the semiconductor device should be updated to “System & Design Integration (S&DI).” S&DI will provide the needed feedback to launch a new field of clear applications, based on a total system solution with innovative design, fabrication, inspection and evaluation equipment. 3D-LSI and S&DI will have a tremendous impact on the future electronics industries.

Keywords

microelectronicspackaginglithography (deposition)
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y05-02
Copyright
Copyright © Materials Research Society 2007

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References

REFERENCES

1. Dennard, R. H. et al, IEEE J. Solid-State Circuits, SC–9, 256 (1974).Google Scholar
2. Available: Intel Developer Forum Fall 2006.Google Scholar
3. Iwai, H., STARC Symposium, pp.27, 2002.Google Scholar
4. Wakabayashi, H. et.al., IEDM Tech. Dig., pp.989, 2003.Google Scholar
5. Thean, A.V-Y. et. al., Symp. on VLSI Technology., pp.164, 2006.Google Scholar
6. Chen, X. et.al., Symp. on VLSI Technology., pp.74, 2006.Google Scholar
7. Available: http://www.itrs.net.Google Scholar
8. Elmore, W. C., J. Appl. Phys., 19, 55 (1948).Google Scholar
9. Nihei, M. et.al., Jpn. J. Appl. Phys. 42, 721 (2003).Google Scholar
10. Gomi, S. et al., IEEE Custom Integrated Circuits Conf., pp.325, 2004.Google Scholar
11. Swtikes, M. and Rothchild, M., J. Vac. Sci. Technol. B19, 2353 (2001).Google Scholar
12. Eimori, T., SEMI Forum Japan 2006, pp.6, 2006 (in Japanese)..Google Scholar
13. Ikeda, et al., SEMI STS symposium 2005, pp.9–40, 2005.Google Scholar
14. Solid State Technol. pp.30, June 2006.Google Scholar
15. Morrow, P. et al., IEEE Electron Device Lett., 27, 335 (2006).Google Scholar
16. Okamoto, K., IEICE trans. on electronics, J88–C, 839, 2005 (in Japanese).Google Scholar
17. Andrews, J. and Baker, N.; IEEE Micro, 26, 25 (2006).Google Scholar