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Fabrication and Properties of Single, Double, and Triple Gate Polycrystalline-Silicon Thin Film Transistors

Published online by Cambridge University Press:  22 February 2011

R. E. Proano  and
R. J. Soave
R. E. Proano
Affiliation:
Department of Materials, Science and Engineering, Bard Hall, Cornell University, N.Y. 14853
R. J. Soave
Affiliation:
Nationa;Facility, Knight Laboratory, Cornell University, Ithaca, N.Y. 14853
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Abstract

Polysilicon based Thin Film Transistors (poly-Si TFT's) with superior electrical performance can be achieved by maximizing the number of intrinsic point defect injected into the material during high temperature processing. These point defects will migrate to grain boundaries (GB's), enhance their mobility by facilitating climb, and allow the boundary to achieve a low energy configuration with a minimum of electrically active broken bonds. Proper processing of poly-Si TFT's therefore requires a redesign of the conventional processing cycle where, working with single crystal silicon, one minimizes the concentration of intrinsic point defects which otherwise precipitate out as Oxidation induced Stacking Faults (OSF's).

TFT's were fabricated under nine different processing cycles to study the relationship between device performance and fabrication conditions. Device performance increased with higher gate oxidation temperature, elimination of HCI flow during gate oxidation, post hydrogenation, and multiple gates. Using conventional MOS processing steps only, n-type (p-type) devices were fabricated, which were capable of handling 40 volts VDS with a leakage current of 2×10−11 (6×10−12) A/μm and effective electron (hole) channel mobilities of 130 (50) cm2/Vs.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 106: Symposium G – Polysilicon Films and Interfaces , 1987 , 317
Copyright
Copyright © Materials Research Society 1988

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References

REFERENCES

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