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Integration Challenges for Chemical Mechanical Polishing of Cu/Low-κ Interconnects

Published online by Cambridge University Press:  01 February 2011

Jeffrey A. Lee ,
Mansour Moinpour ,
Huey-Chiang Liou  and
Thomas Abell
Jeffrey A. Lee
Affiliation:
Intel Researcher at MIRAI, Tsukuba, Japan
Mansour Moinpour
Affiliation:
Intel Corp., Santa Clara
Huey-Chiang Liou
Affiliation:
Intel Corp., Santa Clara
Thomas Abell
Affiliation:
Intel Researcher at IMEC, Leuven, Belgium
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Abstract

The drive for improved performance of microelectronic devices has led to the prevalence of copper metallization and the aggressive development of low-permittivity (low-κ) dielectric materials for use as interlayer dielectrics in BEOL interconnect structures. Progressive scaling of metal line widths coupled with the need to incorporate ultra low-κ (ULK) dielectrics, with κ<2.2, presents numerous challenges for integration and reliability. Perhaps the most significant challenge for the 90nm technology node and beyond is successful planarization of Cuinterconnect structures by chemical mechanical polishing (CMP). The present paper will discuss the general integration challenges and key structural reliability issues for chemical mechanical polishing of Cu-interconnects incorporating ULK dielectric materials.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 767: Symposium F – Chemical-Mechanical Planarization , 2003 , F7.4
Copyright
Copyright © Materials Research Society 2003

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