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Low Temperature Plasma Etching of Copper for Minimizing Size Effects in sub-100 nm Features

Published online by Cambridge University Press:  01 February 2011

Nagraj S Kulkarni
Affiliation:
kulkarnins@ornl.gov, Oak Ridge National Laboratory, Materials Science & Technology, 1 Bethel Valley Road, P.O. Box 2008, MS-6063, Oak Ridge, TN, 37831-6063, United States
Prabhakar Tamirisa
Affiliation:
prabhakar.tamirisa@chbe.gatech.edu, Georgia Institute of Technology, School of Chemical and Biomolecular Engineering, 311 Ferst Drive, N.W., Atlanta, Georgia, 30332-0100, United States
Galit Levitin
Affiliation:
galit.levitin@chbe.gatech.edu, Georgia Institute of Technology, School of Chemical and Biomolecular Engineering, 311 Ferst Drive, N.W., Atlanta, Georgia, 30332-0100, United States
Richard J Kasica
Affiliation:
kasicarj@ornl.gov, Oak Ridge National Laboratory, Oak Ridge, TN, 37831, United States
Dennis W Hess
Affiliation:
dennis.hess@chbe.gatech.edu, Georgia Institute of Technology, School of Chemical and Biomolecular Engineering, 311 Ferst Drive, N.W., Atlanta, Georgia, 30332-0100, United States
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Abstract

A low temperature plasma etching process for patterning copper interconnects is proposed as a solution to the size effect issue in the resistivity of copper. Key features of this etching process based on a previous thermochemical analysis of the Cu-Cl-H system are discussed. Potential benefits of a subtractive etching scheme based on this process in comparison with the damascene scheme for copper-based interconnect processing in sub-100 nm features are presented in the context of the ITRS roadmap. Preliminary experimental work on plasma etching of Cu thin films using the proposed process is discussed.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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