Hostname: page-component-78c5997874-mlc7c Total loading time: 0 Render date: 2024-11-10T06:36:14.005Z Has data issue: false hasContentIssue false
  • English
  • Français

A Novel Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor Fabricated by using a Selective Side Etch Process

Published online by Cambridge University Press:  01 February 2011

Ta-Chuan Liao ,
Chun-Yu Wu ,
Feng-Tso Chien ,
Chun-Chien Tsai ,
Hsiu-Hsin Chen ,
Chung-Yuan Kung  and
Huang-Chung Cheng
Ta-Chuan Liao
Affiliation:
tcliao.ee92g@nctu.edu.tw, National Chiao-Tung University, Institute of Electronics, 1001 Ta Hsueh Road, Hsinchu, Taiwan 300, ROC, Hsinchu, Taiwan, 300, Taiwan
Chun-Yu Wu
Affiliation:
markwillams78@yahoo.com.tw, National Chung Hsing University, Department of Electrical Engineering, No. 250 Kuo Kuang Rd., Taichung, 402, Taiwan
Feng-Tso Chien
Affiliation:
ftchien@fcu.edu.tw, Feng Chia University, Department of Electronic Engineering, No. 100 Wenhwa Rd., Taichung, 407, Taiwan
Chun-Chien Tsai
Affiliation:
austin.ee90g@nctu.edu.tw, National Chiao Tung University, Institute of Electronics, No. 1001 Ta Hsueh Rd., Hsinchu, 300, Taiwan
Hsiu-Hsin Chen
Affiliation:
gnd.ee93g@nctu.edu.tw, National Chiao Tung University, Institute of Electronics, No. 1001 Ta Hsueh Rd., Hsinchu, 300, Taiwan
Chung-Yuan Kung
Affiliation:
cykung@nchu.edu.tw, National Chung Hsing University, Department of Electrical Engineering, No. 250 Kuo Kuang Rd., Taichung, 402, Taiwan
Huang-Chung Cheng
Affiliation:
hccheng536@mail.nctu.edu.tw, National Chiao Tung University, Institute of Electronics, No. 1001 Ta Hsueh Rd., Hsinchu, 300, Taiwan
Get access

Abstract

A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has higher maximum on-off current ratio of 4.6 e107, and the lower off-state leakage current at VGS = -10 V and VDS = 5V of about 100 times less than that of the conventional one. It is attributed to the additional undoped offset region and the vacuum gap to reduce the maximum electric field at drain junction while ascribed to the sub-gate to maintain the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs).

Keywords

polycrystalmetalMo
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 910: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology – 2006 , 2006 , 0910-A22-11
Copyright
Copyright © Materials Research Society 2006

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] Oana, Yasuhisa, “Current and future technology of low-temperature poly-Si TFT-LCDs,” Journal of the SID, vol. 9, pp. 169–172, 2001.Google Scholar
[2] Stewart, Mark, Howell, Robert S., Pires, Leo, and Hatalis, Miltiadis K., “Polysilicon TFT technology for active matrix OLED displays,” IEEE Trans. Electron Devices, vol. 48, pp. 845–851, 2001.Google Scholar
[3] Werner, K., “The flowering of flat displays,” IEEE Spectrum, vol. 34, pp. 40–49, 1997.Google Scholar
[4] Kawachi, G., “Advanced TFT Technologies for System on Glass,” in IDW Tech. Dig., 2004, pp.384–387.Google Scholar
[5] Fossum, J. G., Ortiz-Conde, A., Shichijo, H., and Banerjee, S. K., “Anomalous leakage current in LPCVD polysilicon MOSFET's,” IEEE Trans. Electron Devices, vol. 32, pp. 1878–1884, 1985.Google Scholar
[6] Yazaki, Masatoshi, Takenaka, Satoshi, and Ohshima, Hiroyuki, “Conduction Mechanism of leakage current observed in Metal-Oxide-Semiconductor Transistors and Poly-Si Thin-Film Transistors,” Jpn. J. Appl. Phys., Part 1, vol. 31, pp. 206–209, 1992.Google Scholar
[7] Xiong, Z., Liu, H., Zhu, C., and Sin, J. K. O., “A novel self-aligned offset-gated polysilicon TFT using high-k dielectric spacers,” IEEE Electron Device Lett., vol. 25, pp. 194–195, Apr. 2004.Google Scholar
[8] Nakazawa, K., Tanaka, K., Suyama, S., Kato, K., and Kohda, S., “Lightly doped drain TFT structure for poly-Si LCD's,” in SID Tech Dig., 1990, pp. 311–314.Google Scholar
[9] Tanaka, Keiji, Nakazawa, Keiji, Suyama, Shiro, and Kato, Kinya, “Characteristics of field-induced-drain (FID) poly-Si TFT's with on/off current ratio,” IEEE Trans. Electron Devices, vol. 39, pp. 916–919, 1992.Google Scholar
[10] Chang, Kow Ming, Chung, Yuan Hung, Lin, Gin Ming, Lin, Jian Hong, and Deng, Chi Gun, “A Novel High-Performance Poly-Silicon Thin Film Transistor with a Self-Aligned Thicker Sub-Gate Oxide near the Drain/Source Regions” IEEE Electron Device Lett., vol. 22, pp. 472–474, 2001.Google Scholar
[11] Park, Joon-ha, and Kim, Ohyun, “A novel self-aligned poly-Si TFT with field-induced drain by the damascene process,” IEEE Electron Device Lett., vol. 26, pp. 249–251, 2005.Google Scholar
[12] Hwang, Han-Wook, Kang, C J, Kim, Yong-Sang, “A novel structured polysilicon thin-film transistor that increases the on/off current ratio,” Institute of Physics Publishing Semiconductor Science and Technology, 2003.Google Scholar
[13] Suzuki, K., “Pixel design of TFT-LCD's for high-quality images,” in SID 92 Dig., pp. 39–42, 1992.Google Scholar
[14] Adams, A. C., VLSI Technology, Sze, S. M., Ed., McGraw-Hill Book Co., Inc., New York, 1988.Google Scholar
[15] ISE User's Manual. Synopsys, Inc.Google Scholar
[16] Yin, Chunshan, Chan, Philp C. H., and Chan, Mansun, “An Air Spacer Technology for Improving Short-Channel Immunity of MOSFETs With Raised Source/Drain and High-k Gate Dielectric,” IEEE Electron Device Lett., vol. 26, pp. 323–325, 2005.Google Scholar
[17] Togo, M.; Tanabe, A.; Furukawa, A.; Tokunaga, K.; Hashimoto, T.; “A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs,” in Symp. VLSI Tech. Dig., 1996, pp.38–39.Google Scholar
[18] Shieh, B.; Saraswat, K.C.; McVittie, J.P.; List, S.; Nag, S.; Islamraja, M.; Havemann, R.H., “Air-gap formation during IMD deposition to lower interconnect capacitance,” IEEE Electron Device Lett., vol. 19, pp. 16–18, 1998.Google Scholar