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Numerical Analysis of Packaging-Induced Failures in Cu/Low-k Interconnects

Published online by Cambridge University Press:  01 February 2011

Aditya Pradeep Karmarkar ,
Xiaopeng Xu ,
Xiao Lin ,
Greg Rollins ,
Victor Moroz  and
Xi-Wei Lin
Aditya Pradeep Karmarkar
Affiliation:
adityap@synopsys.com, Synopsys (India) Private Limited, TCAD DFM Solutions, My Home Tycoon, 4th Floor, Block A,, Begumpet, Hyderabad, 500016, India, +91-40-40331536, +91-40-40133770
Xiaopeng Xu
Affiliation:
Xiaopeng.Xu@synopsys.com, Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
Xiao Lin
Affiliation:
Xiao.Lin@synopsys.com, Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
Greg Rollins
Affiliation:
Greg.Rollins@synopsys.com, Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
Victor Moroz
Affiliation:
Victor.Moroz@synopsys.com, Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
Xi-Wei Lin
Affiliation:
Xi-Wei.Lin@synopsys.com, Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
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Abstract

With decreasing feature sizes for every technology node, multi-level metallization schemes that employ copper interconnects and low-k dielectrics are required to achieve the requisite circuit performance. Here, the effects of the mechanical stresses originating from the packaging process on Cu/Low-k interconnects are assessed. The impact of package defects on interconnect reliability is also analyzed. It is seen that the package reliability varies with underfill mechanical properties. The packaging process introduces global level stresses that propagate to the local, i.e. interconnect, level. Moreover, the package defects also have an adverse impact on the mechanical stresses in the metallization structure. The package defects alter the mechanical stresses in the metal lines and affect the reliability. The complex interaction between packaging process induced stresses, package level defects and mechanical properties of various materials is analyzed in order to create robust interconnect designs.

Keywords

packagingthermal stressesstress/strain relationship
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1079: Symposium N – Materials and Processes for Advanced Interconnects for Microelectronics , 2008 , 1079-N09-09
Copyright
Copyright © Materials Research Society 2008

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References

REFERENCES

[1] Cherault, N., Besson, J., Goldberg, C., Casanova, N. and Berger, M.-H. “Finite element simulation of thermomechanical stress evolution in Cu/low-k interconnects during manufacturing and subsequent thermal cycling,” Proceedings of 35th European Solid-State Device Research Conference (ESSDERC 2005), pp. 493–496, Sept. 2005.Google Scholar
[2] Zhai, C. J., Ozkan, U., Dubey, A., Sidharth, , Blish, R. C. (II) and Master, R. N., “Investigation of Cu/low-k film delamination in flip chip packages,” Proceedings of 56th Electronic Components and Technology Conference, 2006, pp. 709–717, May-Jun. 2006.Google Scholar
[3] Mercado, L. L. and Sarihan, V., “Evaluation of die edge cracking in flip-chip PBGA packages,” IEEE Transactions on Components and Packaging Technologies, vol. 26, no. 4, pp. 719–723, Dec. 2003.Google Scholar
[4] Mercado, L. L., Sarihan, V. and Hauck, T., “An analysis of interface delamination in flip-chip package,” Proceedings of 50th Electronic Components and Technology Conference, 2000, pp.1332–1337, May 2000.Google Scholar
[5] Fammos-TX Manuals, Synopsys, Inc., March 2008.Google Scholar
[6] Shih, C. F., Moran, B., and Nakamura, T., “Energy release rate along a three-dimensional crack front in a thermally stressed body,” International Journal of Fracture, vol. 30, pp. 79–102, 1986.Google Scholar
[7] Tsai, M.-Y., Lin, Y.-C, Huang, C.-Y. and Wu, J.-D., “Thermal deformations and stresses of flip-Chip BGA packages with low- and high-Tg underfills,” IEEE Transactions on Electronics Packaging Manufacturing, vol. 28, no. 4, pp. 328–337, Oct. 2005.Google Scholar
[8] Xu, X.-P., and Needleman, A., “Numerical simulations of fast crack growth in brittle solids,” Journal of the Mechanics and Physics of Solids, vol. 42, pp. 1397–1434, 1994.Google Scholar