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Overview of Advanced 3D Charge-trapping Flash Memory Devices

Published online by Cambridge University Press:  01 February 2011

Hang-Ting Lue ,
Kuang-Yeu Hsieh  and
Chih-Yuan Lu
Hang-Ting Lue
Affiliation:
htlue@mxic.com.tw
Kuang-Yeu Hsieh
Affiliation:
kenhsieh@mxi.com.tw, Macronix International Co., Ltd., Hsinchu, Taiwan, Province of China
Chih-Yuan Lu
Affiliation:
cylu@mxic.com.tw, Macronix International Co., Ltd., Hsinchu, Taiwan, Province of China
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Abstract

Although conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity. Although charge-trapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the > 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore's law to continue for at least another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail.

Keywords

microelectronicsmemoryelectrical properties
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1250: Symposium G – Materials and Physics for Nonvolatile Memories II , 2010 , 1250-G01-10
Copyright
Copyright © Materials Research Society 2010

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