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Room Temperature Electron Mobility Enhancement in a Strained Si Channel

Published online by Cambridge University Press:  15 February 2011

L. Garchery ,
P. Warren ,
I. Sagnes  and
P. A. Badoz
L. Garchery
Affiliation:
France Telecom - CNET, BP 98, 38243 Meylan Cedex, FRANCE
P. Warren
Affiliation:
France Telecom - CNET, BP 98, 38243 Meylan Cedex, FRANCE
I. Sagnes
Affiliation:
France Telecom - CNET, BP 98, 38243 Meylan Cedex, FRANCE
P. A. Badoz
Affiliation:
France Telecom - CNET, BP 98, 38243 Meylan Cedex, FRANCE
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Abstract

During the last few years, Si/SiGe heterostructures have been used by several groups worldwide in order to achieve high-mobility two-dimensional electron gases.1-3 To confine high-mobility electrons, these heterosystems are grown in such a way that the Si channel, epitaxially grown on a relaxed SixGe1−x buffer, undergoes a tensile strain. As such structures have a significant conduction band offset, the spatial separation of ionized dopant atoms from mobile carriers can be exploited. The confined electrons in the Si channel are then provided by a doped SiGe supply layer. The significant improvement in SiGe buffer quality has led to low temperature mobilities exceeding 100 000 cm2/Vs with best values above 350 000 cm2/Vs.2-5 However, for MOS applications, the most interesting point is the room temperature (RT) mobility of confined electrons in the Si channel. With this aim in view, RT-mobilities between 2000 and 2600 cm2/Vs have been reported.6 These values are more than twice larger than these of commercial MOSFETs and are also higher than the bulk mobility of intrinsic Si. However, these relatively high values are still lower than the predicted ones (3000 cm2/Vs).7 This is partially due to the fact that the RT-mobility measured on modulation doped heterostructures (MDHs) is never exactly that of the confined electrons in the Si channel. The conduction electrons are in fact not completely transferred from the supply layer to the channel. The latter is the primary and desired path for conduction, but the supply layer can become a second, parallel path, with a lower mobility because of donor impurities. Different methods can be used to reduce the contribution of this parallel path. First, the supply layer can be designed with the lowest possible doping level so as to ensure an almost complete electron transfer at room temperature.8 Secondly, gated Hall devices can be fabricated using Schottky or Metal-Insulator-Semiconductor gates.9-11 These devices allow both the electron density and electron mobility in the strained Si channel to be measured for low gate voltage.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 379: Symposium C – Strained Layer Epitaxy–Materials, Processing, and Devise Applications , 1995 , 321
Copyright
Copyright © Materials Research Society 1995

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References

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