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Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking

Published online by Cambridge University Press:  01 February 2011

Takafumi Fukushima ,
Tetsu Tanaka  and
Mitsumasa Koyanagi
Takafumi Fukushima
Affiliation:
fukusima@sd.mech.tohoku.ac.jp, Tohoku University, United States
Tetsu Tanaka
Affiliation:
ttanaka@sd.mech.tohoku.ac.jp, Tohoku University, Sendai, Japan
Mitsumasa Koyanagi
Affiliation:
sdlab@sd.mech.tohoku.ac.jp, Tohoku University, Sendai, Japan
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Abstract

We have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide high-throughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 micron on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 sec by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.

Keywords

self-assemblyliquidchemical vapor deposition (CVD) (deposition)
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1112: Symposium E – Materials and Technologies for 3-D Integration , 2008 , 1112-E02-07
Copyright
Copyright © Materials Research Society 2009

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References

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