Through-Wafer Polysilicon Interconnect Fabrication with In-Situ Boron Doping

Abstract

Bulk micromachining technology can be used to produce conducting through-wafer polysilicon interconnects, i.e., polysilicon via plugs. This paper presents the process fabrication steps of polysilicon via plugs with in-situ boron doped polysilicon material in order to develop fast one-step doping process, without additional diffusion. The via holes can be processed by high-aspect ratio silicon etching with inductively coupled plasma (ICP). Only one deep ICP etching is required if the wafer is mechanically ground (from the backside) to reduce the wafer thickness of 500 microns to a typical of 400, in order to overcome deep etching sidewall profile problems. After hole formation with ICP the via plug fabrication process continues by growing an insulating thermal oxide layer with a thickness of the order of a micron, followed by an in-situ boron doped LPCVD polysilicon growth to fill the holes with sufficient step coverage. The polysilicon growth temperature at 680°C ensures sufficient step coverage, reasonable furnace process time and enables planarization processing, such as grinding and chemical-mechanical polishing (CMP). The subsequent planar processing typically requires planarization of the polysilicon layer down to the original silicon (or oxide) surface with CMP, and some doping activation step, which usually can be performed together with some additional oxidation step. Applications of the via plugs in the field of silicon-based sensors or actuators enable significant reduction of the front surface wiring density, which opens additional space for denser packing or other desired components.