In this paper, an electromagnetic (EM) simulation assisted parameter extraction procedure is demonstrated for accurate modeling of down-scaled transferred-substrate InP HBTs. The external parasitic network associated with via transitions and device electrodes is carefully extracted from calibrated three-dimensional EM simulations up to 325 GHz. Following an on-wafer multi-line Through-Reflect-Line calibration procedure, the external parasitic network is de-embedded from the transistor measurements and the active device parameters are extracted in a reliable way. The small-signal model structure augmented with the distributed parasitic network provides accurate small-signal prediction up to 220 GHz.
