This paper discusses the design steps and experimental characterization of a monolithic microwave integrated circuit (MMIC) power amplifier developed for the next generation of K-band 17.3–20.2 GHz very high throughput satellites. The technology used is a commercially available 100-nm gate length gallium nitride on silicon process. The chip was developed taking into account the demanding constraints of the spacecraft and, in particular, carefully considering the thermal constraints of such technology, in order to keep the junction temperature in all devices below 160°C in the worst-case condition (i.e., maximum environmental temperature of 85°C). The realized MMIC, based on a three-stage architecture, was first characterized on-wafer in pulsed regime and, subsequently, mounted in a test-jig and characterized under continuous wave operating conditions. In 17.3–20.2 GHz operating bandwidth, the built amplifier provides an output power >40 dBm with a power added efficiency close to 30% (peak >40%) and 22 dB of power gain.

A 24 GHz low-power transceiver is designed, fabricated, and characterized using 130 nm complementary metal-oxide semiconductor (CMOS) process. The designed transceiver is targeted for frequency-modulated-continuous-wave (FMCW) wireless local positioning. The transceiver includes four switchable receiving channels, one transmitting channel and local-oscillator generation circuitries. Several power-saving techniques are implemented, such as switch channel and adaptive mixer biasing. The design aspects of the low-power circuit blocks and integration considerations are presented in details. The integrated transceiver has a chip area of only 2.2 mm × 1.7 mm. In transmitting mode the transceiver achieves an output power of 4 dBm and phase noise of −90 dBc/Hz at 1 MHz, while consuming 75 mW power consumption under 1.5 V power supply. In switch-channel receiving mode the transceiver demonstrates 31 dB gain and 6 dB noise figure with 65 mW power consumption. The transceiver measurements compare well with the simulated results and achieve state-of-the-art performance with very low-power consumption.

The use of 130-nm CMOS for power amplifiers at 20 GHz is explored through a set of power amplifiers as well as transistor level measurements. The power amplifiers explore single versus cascode configuration, smaller versus larger transistor sizes, and the combination of two amplifiers using power splitters/combiners. A maximum output power of 63 mW at 20 GHz was achieved. Transistor-level characterization using load pull measurements on 1-mm gate width transistors yielded 148-mW/mm output power. Transistor modeling and layout for power amplifiers are also discussed. An estimate on the maximum achievable output at 20 GHz from 130-nm CMOS power amplifiers, based on findings in this paper and the literature, is finally presented.