In this paper, we address the architecture of a multi-antenna receiver and we aim at reducing the complexity of the analog front-end. To this end, an innovative architecture is introduced based on code multiplexing. This architecture uses the direct sequence spread spectrum technique in order to multiplex the different antennas contributions through a single In-phase/Quadrature (IQ) demodulator. Simulation and measurement results show that the bit error rate does not increase so much with the multiplexing in both Gaussian and fading environments and with strong radiofrequency (RF) defaults conditions. The complexity evaluation shows that the proposed architecture significantly reduces the chip area and the power consumption of the front-end.
