Antenna arrays are a main driver of next generation millimeter-wave communication and radar systems as shrinking antenna sizes leverage larger arrays to compensate for reduced link budget. However, conventional phase controlled arrays exhibit a frequency dependent scan angle that appears as loss to a fixed counterpart. Bandwidth limitations introduced by the so-called beam squint effect hinder larger array sizes and data rates thereby generating a demand for timed arrays as a solution. This paper gives a quantified overview of the beam squint phenomenon, different hardware architectures as well as evaluation parameters and common shortcomings of true-time delay (TTD) elements. A broad variety of TTD realizations from literature are compared by their operational principles and performance. Finally, the delay interpolation principle, its non-idealities, and their impact on a hierarchically time delay controlled D-band antenna array are described. Extended content on a previously published, continuously tunable TTD implementation at a center frequency of 144 GHz with a bandwidth of 26 GHz and a delay range of 1.75 ps that requires only 0.53 × 0.3 mm2 of core chip area is presented. Measurement results have been obtained from a demonstrator manufactured in 130 nm BiCMOS technology.

This paper presents a systematic comparison of the relationship between transmission line characteristic impedance and Q-factor of CPW, slow-wave CPW, microstrip, and slow-wave microstrip in the same CMOS back-end-of-line process. It is found that the characteristic impedance for optimal Q-factor depends on the ground-to-ground spacing of the slow-wave transmission line. Although the media are shown to be similar from a mode of propagation point of view, the 60-GHz optimal Q-factor for slow-wave transmission lines is achieved when the characteristic impedance is ≈23 Ω for slow-wave CPWs and ≈43 Ω for slow-wave microstrip lines, with Q-factor increasing for wider ground plane gaps. Moreover, it is shown that slow-wave CPW is found to have a 12% higher optimal Q-factor than slow-wave microstrip for a similar chip area. The data presented here may be used in selecting Z0 values for S-MS and S-CPW passives in CMOS that maximize transmission line Q-factors.

A 77-GHz–directional folded dipole antenna integrated in an embedded wafer level ball grid array package is presented. For the characterization of the antenna, a frequency multiplier is embedded, which scales the 4.25-GHz input signal up to 76.5 GHz and allows the use of a commercial signal source. The antenna structure is manufactured at the metallic layer, in the fan-out area of the package, and is directly connected to the monolithically integrated transceiver. The gain of the antenna is about 7 dBi, measured over a large bandwidth of about 8 GHz. The combination of the frequency multiplier with a 77-GHz transceiver and the on-package antenna is a promising approach for a system-in-package to future radar modules for automotive radar applications. Such a module avoids 77-GHz transitions to the printed circuit board and hence simplifies the design and manufacturing of the radar sensor significantly.

The design of a subharmonic downconverter for 94-GHz imaging arrays in SiGe:C technology is presented. A three-stage differential low-noise amplifier (LNA) with lumped matching networks is used together with a subharmonic mixer driven by a single-pole local-oscillator poly-phase network to form the front-end. The LNA yields 15 dB gain at 94 GHz, while the mixer provides 5 dB conversion gain over a 10 GHz IF bandwidth. The integrated downconverter provides 20 dB conversion gain at 94 GHz with an input 1-dB compression point of −31 dBm and has a current consumption of 45 mA at a 3.3 V supply voltage. The total required die area of the complete downconverter (excluding pad frame) is 0.1 mm, thus making it particularly suitable as a front-end in multi-channel receiver systems.