As a first step in the identification of suitable alternative gate dielectrics for metal oxide semiconductor field-effect transistors (MOSFETs), we have used tabulated thermodynamic data to comprehensively assess the thermodynamic stability of binary oxides and nitrides in contact with silicon at temperatures from 300 K to 1600 K. Sufficient data exist to conclude that the vast majority of binary oxides and nitrides are thermodynamically unstable in contact with silicon. The dielectrics that remain are candidate materials for alternative gate dielectrics. Of these remaining candidates, the oxides have a significantly higher dielectric constant (ĸ) than the nitrides. We then extend this thermodynamic approach to multicomponent oxides comprising the candidate binary oxides. The result is a relatively small number of silicon-compatible gate dielectric materials with ĸ values substantially greater than that of SiO2 and optical bandgaps ≥ eV.

Continued scaling of microelectronic devices is demanding that alternatives to SiO2 as the gate dielectric be developed soon. This in turn has placed enormous pressure on the abilities of physical characterization techniques to address critical issues such as film and interface structure and composition, transport properties, and thermal or chemical stability. This article summarizes the strengths and capabilities of four techniques used for the materials characterization of alternative gate dielectrics: scanning transmission electron microscopy (STEM) in conjunction with electron energy-loss spectroscopy (EELS), medium-energy ion scattering (MEIS), infrared-absorption spectroscopy (IRAS), and x-ray photoelectron spectroscopy (XPS). The complementary nature of these techniques has allowed for a detailed picture of the various properties of alternative gate dielectrics, and in particular of the dielectric/silicon interface. Critical issues and features of several important alternative gate dielectrics, ZrO2, AI2O3, Y2O3, and Gd2O3, are explored in light of the well-studied SiO2/Si system.

In addition to meeting the formidable challenges of replacing the nearly perfect SiO2 dielectric, a new dielectric ideally needs to replace SiO2 with minimal rearrangement of the complementary metal oxide semiconductor (CMOS) process flow. In this article, we outline the essential materials-integration issues that arise out of the technical requirements for minimizing changes to future process technologies. These include interfacial layer formation, film microstructure, deposition technologies, and electrical performance challenges such as trapped charge and the mobility degradation associated with any replacement material. Integration of the high-ĸ materials currently under consideration presents a significant challenge for materials scientists and engineers in industry and academia.

We address current challenges in the fundamental understanding of physical and chemical processes that occur in the fabrication of the transistor gate stack structure. Critical areas include (1) the interface between bulk silicon and high-dielectric-constant (high-ĸ) insulators, (2) the interface between high-ĸ insulators and advanced gate electrodes, and (3) the internal interfaces that form within dielectric stacks with nonuniform material and structure compositions. We approach this topic from a fundamental understanding of bonding and electronic structure at the interfaces, and of film-growth kinetics in comparison with thermodynamics predictions. Implications for the dielectric/electrode interface with metallic gates and issues with integration will also be presented.

The continual scaling of complementary metal oxide semiconductor (CMOS) technologies has pushed the Si-SiO2 system to its very limits and has led to the consideration of a number of alternative high-ĸ gate dielectric materials. In the end, it will be the electrical properties of the new Si/high-ĸ system that will determine its usefulness in future CMOS generations. For this reason, the study of the electrical properties of high-ĸ gate insulators is crucial. We present an overview of some of the electrical characterization techniques and reliability tests used to evaluate possible high-ĸ gate materials. Most of these techniques are well known from the characterization of SiO2 layers, but there are some additional complications, such as the presence of several different layers within one gate stack or the use of different gate electrode materials. These make the interpretation and comparison of experimental results more troublesome.

This brief article sets the context for the March 2002 issue of MRS Bulletin focusing on Alternative Gate Dielectrics for Microelectronics. Contributors are several experts from industry and academia engaged in the search for manufacturable solutions for a suitable alternative gate dielectric to SiO2 using high-dielectric-constant (high-ĸ) materials. Issues discussed in the articles include thermodynamics criteria for materials selection, materials interactions in the construction of the transistor gate stack, characterization of alternative materials, determination of suitable band offsets for candidate dielectrics, and integration of these alternative gate dielectrics in a manufacturable environment.