It has demonstrated to exploit various layout effects of advanced strained engineering to enhanced the performance of nano-scaled transistors. In actual fabrications, the gate framework usually protrudes out to the channel area even over the spuriously diffused active region, over the soft shallow trench isolation region. The foregoing device feature is interesting and critical when enhancing and managing mobility gain are taken into account by used mechanics and induced strained silicon technology in narrow scale channel widths devices. Thus, a silicon-based 22 nm p-type MOSFET combined stressors of a source/drain Si75Ge25 alloy and a -2 GPa compressive contact etch stop layer with different protrudent gate widths to investigate this issue. The fabricated oriented stress simulation extracted stress component within the device channel to estimate and analyze the performance of mobility gain and stress contours for the concerned nanoscale device.
