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Spin-On Glass Films in Multilevel Ic Interconnection

Published online by Cambridge University Press:  21 February 2011

Satish K. Gupta
Satish K. Gupta*
Affiliation:
Allied-Signal Inc., Planarization and Diffusion Products, 1090 S. Milpitas Blvd., Milpitas, CA 95035
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Abstract

Among the variety of techniques available today for interlevel dielectric planarization, techniques based on spin-on glass (SOG) films are relatively attractive because of process simplicity and minimal equipment requirements. This paper reviews the materials and processes of SOG technology as it is applied in dielectric planarization. The SOG planarization schemes employ SOG films either as a permanent part of the interlevel insulation layer or as a sacrificial layer in the ‘etch-back” techniques. The properties of the various types of comnircially available SOG materials are discussed in relation to their functional and processing characteristics.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 108 , 1987 , 275
Copyright
Copyright © Materials Research Society 1988

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References

REFERENCES

1.Armstrong, W. E. and Tolliver, D. C., J. Electrochem. Soc. 121, 307 (1974).Google Scholar
2.Kern, W. and Schnable, L., RCA Review 43, 423 (1982).Google Scholar
3.Desbiens, D., Electrochem. Soc. Ext. Abs. 84(2), 605 (1984).Google Scholar
4.Kotani, H., Yakushiji, H. and Harada, H., J. Electrochem. Soc. 130(3), 645 (1983).Google Scholar
5.Mogami, T., Morimoto, M., Okabayashi, H. and Nagasawa, E., J. Vac. Sci. Technol. 3(3), 857 (1985).Google Scholar
6.Machida, K. and OikawA, H., J. Vac. Sci. Technol. B 464, 818 (1986).Google Scholar
7.Mercier, J. S., Naguib, H. M., Ho, V. Q. and Nentwich, H., J. Electrochem. soc. 132(5), 1219 (1985).Google Scholar
8.Adams, A. C., Solid State Technol. 24, 178 (1981).Google Scholar
9.Rothman, L. B., J. Electrochem. Soc. 130, 1131 (1983).Google Scholar
10.Vines, L. B. and Gupta, S. K., Proc. IEEE VLSI Multilevel Interconn. Conf., 506 (1986).Google Scholar
11.Chu, J. K., Multani, J. S., Mittal, S. K., Proc. IEEE VLSI Multilevel Interconn. Conf., 474 (1986).Google Scholar
12.Hazuki, Y. and Moriya, T., Proc. IEEE VLSI Multilevel Interconn. Conf., 121 (1986).Google Scholar
13.Gupta, S. K. and Chin, R. L., ACS Symp. Ser 295, 349 (1986).Google Scholar
14.Schmidt, H., Mat. Res. Soc. Symp. Proc. 32, 327 (1984).Google Scholar
15.Rey, A., Lafond, D., Mirabel, J. M., Tacussel, M. C. and Coster, M. F., IEEE VLSI Multilevel Interconn. Conf., 491 (1986).Google Scholar
16.Parekh, N., Allen, R., Yao, W. and Fulks, R., Electrochem. Soc. Ext. Abs. 86–2, 530 (1986).Google Scholar
17.Pai, P., Oldham, W. G. and Ting, C. H., IEEE VLSI Multilevel Interconn. Conf., 364 (1987).Google Scholar
18.Brewer, R. M. and Gasser, R. A. Jr., IEEE VLSI Multilevel Interconn. Conf., 376 (1987).Google Scholar
19.Tui, M. D., Streif, T. A., Schoenberg, K. E., Dorrance, R. H. and Proctor, P. P., IEEE VLSI Multilevel Interconn. Conf., 385 (1987).Google Scholar
20.Lubic, K. G., Blodgett, J. L. and Gupta, S. K., Electrochem. Soc. Ext. Abs. 87–2, 645 (1987).Google Scholar