Packaging technology must deal with the inexorable trend of semiconductor technology towards higher levels of integration. Extrapolation of present trends suggests that chips with 100 million devices will be produced by the end of the present century. The ability of technology to miniaturize pin-outs will limit the utilization of all of these devices for purposes other than memory. This limitation plus problems of supplying power and removing heat means that chips for high-performance large systems, where the demand for pins follows a well known rule, will probably be limited to levels of integration less than 100,000. A model of large system wiring shows that large increases in the density of wires in system packages and in the rate at which heat can be removed will be needed.

Less severe limitations apply to low cost applications. No large increase in power per chip can be anticipated. However, more powerful microprocessors will become available and will need increased amounts of input-output capability.

Microminiaturization is desirable for reasons of lower cost, lower volume and weight, higher performance, and higher reliability. Microminiaturization is best achieved by downscaling the feature sizes on the chip itself, and this indeed continues to be the major driving force in the electronics revolution. It is normally cheaper, weighs less, is faster, and is more reliable to put as much of a system's interconnection effort on the chip itself (i.e., packaging level 0). Costs increase steeply for interconnections on the higher levels.

New, high temperature superconducting materials could eventually be used for interconnections in electronic systems. Such interconnections would undoubtedly cost more to implement than conventional ones, so the most likely applications would be for complex, high-speed systems that could benefit from the performance advantages of a resistance-free interconnecting medium. The problem with conventional conductors in these systems is that the resistance of wires increases quadratically as dimensions are scaled down. The most important advantage offered by superconductors is that they are not linked to this scaling rule. Their principal limitation is the maximum current density that they will support and this determines the range of applications for which they are superior to conventional conductors. An analysis will be presented which examines the relative advantages of superconductors for different critical current densities, wire dimensions and system sizes.

If their critical current densities are adequate, and if they can statisfy a number of processing criteria, then superconductors could find useful applications in a number of high performance electronic systems. The most likely applications will be those demanding very high interconnection densities. Several of these systems will be discussed.

We have used synchrotron x-ray topographic techniques to study the stresses in thin films formed upon silicon substrates either by evaporation or sputtering. It is found that the film stress generally decreases with increasing film thickness for evaporated films, but film delamination occurs at a well defined film thickness. Transmission electron microscope studies have been performed on the same specimens in order to reveal what mechanisms are involved with the delamination of the films.

During the processing and packaging of silicon integrated circuits there are many sources of die stress. Probably the least understood and controlled is the stress introduced during the die attach and molding processes. The largest packaging stresses are due to the mismatch of the thermal expansion coefficients between the leadframe and the die,and the die and the molding material. We report results obtained by monitoring the resistance changes of implanted, p-type resistors, undergoing various heat treatments with a matrix of mold and leadframe materials.

The interdiffusion and crystallization reactions between amorphous Ni-Nb alloy films and Si substrates and several overlayer metals have been monitored by x-ray diffraction and high resolution Rutherford backscattering spectroscopy. Free standing amorphous thin films of Ni-Nb alloys crystallize in one hour at temperatures between 600–625 °C and show little dependence of the crystallization temperature, Tx, on composition over the range from 30–80 at.% Ni. However, in films that are sputter deposited onto Si substrates Tx tends to increase with increasing Nb composition. Ni60Nb40 samples without overlayers crystallize at 650–700 °C. Enhancement of the thermal stability to 700–750 °C is achieved with a Nb overlayer. In contrast, a Ni overlayer can reduce Tx to 450 °C. At the film/substrate interface silicide formation reactions with Ni from the film contribute to a destabilization of the amorphous alloy. The modification of Tx with Ni, Nb, and other overlayers appears to be related to changes in the reaction kinetics associated with penetration of the overlayer into the film.

A high-energy (MeV) helium ion beam has been focused down to 1 μm by a combination of piezo-driven objective slits and a magnetic quadrupole doublet. Rutherford backscattering (RBS) mapping techniques using focused MeV ion beams were, for the first time, applied to multilayered structures of metals, isolated with insulators, representing a test structure for multilayered wiring or interconnections of integrated circuits to nondestructively analyze the imperfection of the structures.

Ten years ago, the conventional wisdom as cited by Rex Rice and others was that interconnect wiring on a silicon chip was much less expensive than interconnections on a ceramic hybrid, a printed circuit board, or cable interconnect. That led to a major emphasis on increasing the size and complexity of the silicon chip, with the other interconnect media left for the overflow or leftovers that could not be placed on the chip.

A major change of thinking was triggered by Knausenberger and Schaper of AT&T (1), with the realization that costs normalized per inch of wire length were nearly identical for all forms of interconnect. Literally an inch of interconnection circuit costs the same whether that circuit was on silicon or on ceramic, whether that circuit was on a printed circuit board or in cable.

If the only important criteria is the length of the interconnect, then a system or a board of the smallest size and area for a given circuit will have the shortest path lengths and the lowest cost. The dominant criteria is the area of the interconnection medium that carries the active silicon.

A high-performance packaging technology being developed at Honeywell and a number of other companies uses thin-film processes to pattern high-density interconnections in multiple layers of a high-conductivity conductor (e.g., copper) and a polymer dielectric, primarily polyimide. This paper describes the physical characteristics and unique advantages of this thin film multilayer (TFML) interconnect technology; it then summarizes the results of recent work done at Honeywell in processing TFML structures, assessing the stability and reliability of the materials system, and fabricating test vehicles and demonstration packages.

Among the available packaging technologies, thin film wiring is most suitable for high density package applications. This paper discusses the materials choices for the thin film wiring and some possible fabrication processes. The Cu- polymer or Cu- glass system are most promising from both performance and manufacturability perspectives. The interface adhesion and high inter layer interconnection resistance are critical problems for this structure. The use of a Cr, Cu blend structure as an interface layer will solve this problem. The microstructure, interface chemistry and the adhesion mechanisms of this blend layer are discussed.

Silicon carbide materials with BeO addition (2 wt%) have the unique properties of high electrical resistivity, high thermal conductivity, and a thermal expansion coefficient close to that of silicon. The materials have been used as a chip carrier material for high power LSI packaging. Microstructures were correlated by means of analytical electron microscopy (AEM), with the physical properties. Generally, BeO particles are evenly distributed mostly at triple points and the grain growth is anisotropic and many grains are elongated with an aspect ratio of 2 or 3. The average grain size is measured to be around 5 μm and the morphology is typically thick tabular.

AEM analysis has shown that large middle section of each SiC grain is mostly 6H polytype with a few or no stacking faults. On both sides of the 6H polytype, sheaths are formed, which consist of a large number of extremely thin 4H or other polytype lamellae. Along grain boundaries, no second phase formation is observed with a few exception of Be 2 C and impurity transition metal compounds lamellar formation.

The results indicate that direct and clean contacts between 6H lamellae and BeO grain or other 6H lamellae form a path of high thermal conductivity. On the other hand, complex network of thin disordered (4H rich) lamellae doped with BeO forms the electrically high resistive path.

As the performance requirements of ceramic components are refined, the demands placed on the materials used in their processing also become more stringent. For example, in advanced ceramic packaging applications, it is increasingly important that the organic polymers used as binders be capable of degradation and removal at low temperatures and in non-oxidizing atmospheres. This paper examines the chemistry that can occur during two fundamental stages of the binder removal process, (1) the breakdown of the C–C backbone of the polymer during pyrolysis, and (2) the interaction of the small molecules that are produced during pyrolysis with ceramic surfaces. The work has focused on acrylate and methacrylate systems, both because this is an important family of polymers for applications in tape casting, and because there is a relatively extensive literature on their pyrolysis chemistry.

The need for low dielectric constant, high thermal conductivity, matched thermal expansion and co-processability in electronic substrates is reviewed. Since no single phase material is able to satisfy all the requirements, a microscopic composite approach is proposed. Recent experimental evidence supporting the concept is also presented.

The Ti/Al2O3 system is being considered for advanced aerospace applications and is important in microelectronics where Ti is used for metallization on Al2O3 substrates. We have studied the intrinsic reactivity of Ti with the R-plane (1012) surface of α-Al2O3 by x-ray photoemission spectroscopy (XPS) and transmission electron microscopy (TEM) techniques. XPS results indicate that a for deposition of several monolayers of Ti at 25 °C, the Ti reduces the Al2O3 surface to produce Ti-O bonds. At 1000 °C the Ti reduces the Al2O3 to produce Ti-O and Ti-Al bonds. Cross-section TEM specimens were prepared from 200 nm thick Ti films deposited on Al2O3 at 25 and 800 °C to observe the interface region. In samples deposited at 25 and 800 °C, without further annealing, no reaction zone could be seen in the TEM. Ordered Ti3Al (78 ± 5 Ti, 16 ± 3 Al and 6 ± 3 0 wt pct) was observed in a sample deposited at 25 °C and annealed at 800 °C for 2 hours.

Thermal expansion coefficients (TECs) for polyimides differ very much depending on their chemical structures. Polyimdes with a rod-like structure as their backbone chains have lower TEC values. This is attributed to restraining of thermal expansion by rod-like molecules within intermolecular spaces, analogous to glass fibers in FRPs. The development of new polyimides which can closely match TECs of inorganic materials, such as metal or Si, can eliminate problems produced by thermal stress including warping, cracking or delamination.

A new multilevel interconnection system using multilayered dielectrics consisting of low thermal expansion polyimide and inorganic materials has been proposed as one future technology for submicron VLSIs. Consequently, adhesiveless, high quality flexible printed circuit boards have been developed using a polyimide with the same TEC as copper foil. Their most significant property is a high dimensional stability after heat treatments, such as in a soldering process. Furthermore, they have very high adhesion strength at elevated temperatures.

The printed circuit board is an integral part of the electronic packaging hierarchy. Its use began more than 40 years ago, and the demand for printed circuit boards has increased in parallel with the growth of the electronics industry.[1] According to a recent forecast, the worldwide production of printed circuit boards will reach to over 19 billion U.S. dollars' worth by 1990.[2] With continuing demands for more interconnections, the multilayer circuit board industry is experiencing its fastest growth rate. Boards with more than 20 inner planes of circuitry are being manufactured with high reliability.

Based on dollar values, more than 90% of the circuit boards produced are in the rigid board category, where starting materials are based on thermosetting prepregs produced by a solution impregnation method. This article is a review of materials currently used in rigid composites.

During the past five years, the computer you bought with 128 Kbytes of memory has been upgraded by the availability of 40 Mbyte storage and modems which allow instant access to databases around the world. The continuing need to perform more complex missions for modern defense systems in more hazardous environments will call for substantially higher data rates than are available today.

The selection of the proper resin system for a molded PWB or electronic package must take into account considerably more parameters than simply the cost of and the ability of the polymer to fill the tooling. Molding of an electronic package is only the initial step in a multi stage sequence to produce a functional PWB or interconnect device.

It is of extreme importance that a manufacturer of molded electronic packages understand not only the fabrication properties of a resin, but also those mechanical, thermal, and chemical requirements of the circuit application and assembly operations.

A specific circuitry application process will usually require a specific set of substrate characteristics. These performance characteristics may relate to platability, thermal stability, modulus, compressive strength, or even adhesive bondability for a given procedure. The substrate requirements for several popular circuit application methods is reviewed.

Assembly presents perhaps the most demanding area of resin performance in electronic package or PWB fabrication. The thermal stresses encountered in wave soldering and vapor phase reflow will quickly differentiate among current engineering resin offerings. The importance of controlled moisture absorption and high temperature modulus retention is explored in addition to end use environmental factors which can be of special concern.

The state of the art for the printed circuit (pc) industry is the Surface Mount Technology (SMT) using leadless ceramic chip carriers (LCCCs). The SMT technique is used to design, fabricate, and assemble affordable high-speed, high-density electronic modules with reduced size and weight. However, to take full advantage of the SMT, new high-performance printed circuit board (PCB) substrate materials must be developed, especially if the goal is to satisfy the high reliability required in military applications. The most critical requirement is matching the in-plane coefficient of thermal expansion (CTE) with the SMT-PCB's and the chip carriers (LCCCs) to reduce the solderjoint stresses during thermal cycling. Solder-joint reliability can be improved significantly by tailoring the in-plane CTE to approximately 6–7 ppm/°C (of the alumina chip carrier) using Kevlar and/or quartz fabric-reinforced polymer composites, instead of conventional glass composites. Less attention has been focussed on other important requirements, e.g., out-of-plane (Z-axis) expansion, glass transition temperature (Tg), dielectric constant, and resin microcracking, which also play important roles in the overall performance of the substrate materials. For example, high Z-expansion puts additional strain on the plated through holes (PTH), thereby affecting PTR reliability. A low Tg significantly increases the amount of thermal stress imposed during thermal cycling on solder joints and PTH, and leads to failures. This paper contains a brief review of the requirements of a SMT-PCB substrate material, including such critical parameters as: in-plane CTE, out-of-plane CTE, Tg, dielectric constant, fiber-to-resin ratio, and resin microcracking, and their effects on solder joint reliability, PTH reliability, dimensional stability, and electrical performance.

The hygrothermal fatigue induces a complex phenomenology in the epoxy composites, with degradation of the linear coefficients of expansion.

Epoxy composites, (novolac type, with SiO2 as filler, 75–85 % in weight) have been exposed to high temperature and high pressure moisture.

A role important is played by the decomposition products formed during the aging. The Molecular Weight Distribution of these species has been followed by GPC and shows that there is partial depolymerization of the matrix after 24 h treatment time. It has been found that there is surface migration of low Molecular Weight species, both additives and decomposition products.