Historically, radiation-induced corruption of data in high-speed complementary metal oxide semiconductor designs has been limited to on-board static random-access memory in various memory caches. Successive generations of scaling, however, have resulted in capacitance reductions in key logic circuits, increasing their vulnerability to these “soft errors.” Charge delivered by radiation events now carries a substantial probability of inducing upsets, not only in bistable elements, but in logic evaluation circuits as well. This article introduces the reader to common logic-circuit topologies in high-speed microprocessors, radiation circuit response mechanisms that can compromise logic evaluation integrity, and existing techniques that mitigate this exposure.

The once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliability-failure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed.

This article approaches single-event upset (SEU) problems from the standpoint of experimental nuclear physics, with a focus on certain neutron experiments and neutron data essential for SEU studies. A review is given of some research programs, both basic and applied, that are strongly motivated by SEU applications. Some specific examples are presented from the The (short for Theodor) Svedberg Laboratory (TSL) in Uppsala, Sweden: First, using the quasi-monoenergetic neutron beam, SEU cross sections (of chips) are measured over the neutron energy range of 20–150 MeV. Data from the same technology generation, in general, can be fitted into a simple curve. Second, the particle origins of SEUs are discussed from the framework of neutron–nucleus spallation reactions.