Despite having an npn epitaxial structure resembling a Si BJT, the switching performance of the SiC Junction Transistor or SJT is purely controlled by its terminal capacitances, similar to a SiC MOSFET or JFET. Further, the absence of a “high-resistance” SiC MOS channel in the SJT means that the SJT’s RON,sp is solely limited by the resistance of the n- drift region. Recently released SJTs feature RON,sp as low as 2 mΩ-cm2 for a breakdown voltage (BV) of 1600 V, and a RON,sp of 2.4 mΩ-cm2, for a breakdown voltage of 2000 V. Current gains > 100 are achieved, even on the highest current SJTs. Unlike Si BJTs, SJTs do not suffer from second breakdown, and can perform under unclamped inductive switching (UIS) conditions, even at full rated collector currents. Near-∞ Early voltage and a negative temperature co-efficient of current gain in a SJT ensure low collector currents under short-circuited load conditions, resulting in short-circuit withstand time as high as 14 µs, even at > 80% of the maximum rated BV. Recent technological developments have significantly improved the stability of the SJT current gain (β) under high-current stress conditions. A 1000-hour long, 200 A/cm2 DC current stress results in only 10% reduction of the current gain (β) during the early stages of the stress test, while the β is perfectly stable for the remainder (>90%) of the stress duration. Similar β compression is observed, whether the collector current stress is applied at DC, or at a high switching frequency ≥ 200 kHz.

Reduction in background carrier concentration has been investigated for 4H-SiC C-face epitaxial growth in order to be applied for ultra-high voltage power devices. Optimizing epitaxial growth parameters made it possible to achieve 7.6x1013 cm-3 as the background carrier concentration within a whole area of specular 3-inch wafers. In addition to the background carrier concentration reduction, epitaxial film thickness variation, surface defect density and the carrier lifetime have been confirmed to fulfill the requirements for the devices.

The temperature dependence of the forward and reverse current voltage characteristics of circular Al+ implanted 4H-SiC p-i-n vertical diodes of various diameters, post implantation annealed at 1950 °C/5 min, have been used to obtain the thermal activation energies of the defects responsible of the generation and the recombination currents, as well as the area and the periphery current component of the current voltage characteristics. The former have values compatible with those of the traps associated to the carbon vacancy defect in 4H-SiC. The hypothesis that only these traps may justify the trend of the current voltage characteristics of the studied diodes has been tested by simulations in a Synopsys Sentaurus TCAD suite.

3C-SiC devices are hampered by a high crystal defect density due to the hetero-epitaxial growth of these films, which results in the presence of stacking faults (SF). In this paper high growth rate CVD processes have been used to try to reduce the SF density in 3C-SiC films. In a first step a high growth rate (30 μm/h) has been used to grow 50 μm thick 3C-SiC layer on (100) Si. Then the silicon substrate was removed via etching and a further 3C-SiC growth was performed with a higher growth rate (90 μm/h) at a higher temperature (1600 °C) to obtain a final thickness of 150 μm. The SF presence and density were evaluated by TEM analysis performed on as-grown samples and SEM analysis on KOH etched samples with various thicknesses. A decrease of SF density was observed with an increase of 3C-SiC film thickness, with the best results (500/cm) obtained for the thickest sample. The 3C-SiC film quality and orientation was evaluated by XRD are correlated with film thickness and SF density.

The cubic polytype of silicon carbide is a stimulating candidate for Micro-Electro-Mechanical-Systems (MEMS) applications due to its interesting physical and chemical properties. Recently, we demonstrated the possibility to elaborate 3C-SiC membranes on 3C-SiC pseudo-substrates, using a silicon epilayer grown by Low Pressure Chemical Vapor Deposition as a sacrificial layer. Such structures could be the starting point for the elaboration of new MEMS devices. However, the roughness still represents a major concern. Therefore, in this contribution, we investigate the influence of an excimer laser irradiation on the Si epilayer surface prior to the 3C-SiC epilayer growth. We compare these results with the 3C-SiC epilayer grown directly on the as-grown Si epilayer.

Finite element modelling has been used to optimise the current/ voltage (I/V) characteristics of metal/ n-SiC and metal/ n-Si diodes incorporating a thin interfacial layer. The electrical properties of the diodes have been examined in relation to the polytype of SiC (3H, 4H or 6C), the doping level, NA, (1015 - 1018cm3) of the substrate, the defect state density, Dit and the work function of the Schottky metal, Φm. The modelling by Technology Computer-Aided Design (TCAD) has shown that the presence of an interfacial insulating layer with a thickness of 1.0 nm has reduced the reverse leakage current of the diode by a factor of ∼102 in Si and 1013 (from 10-19 A to 10-6 A) for SiC with only a minor reduction (∼ 0.8 times) in the forward current in SiC. The properties of the diodes have been modelled at room temperature without thermal annealing.