This paper presents the design and implementation of a Chip Scale Atomic Clock (CSAC) driven dual-channel Digitally Configurable Receiver (DCR) for Global Navigation Satellite Systems (GNSS). The receiver is intended to be used for research applications such as; multipath mitigation, scintillation assessment, advanced satellite clock and spatial frame transformation modelling, Precise Point Positioning (PPP) as well as rapid development and assessment of novel circuits and systems for GNSS receivers. A novel sub-Nyquist sampling (subsampling) receiver architecture incorporating dual-band microstrip RF filters is employed in order to minimize the complexity of the multi-frequency Radio Frequency (RF) front-end. Moreover, the digital receiver incorporates a novel and complexity-reduced Fast Fourier Transform (FFT) core for signal acquisition as well as COordinate Rotation DIgital Computer (CORDIC) cores for the code/carrier discriminators in order to minimize the resource allocation on the FPGA. The receiver also provides easy access to enable adjustment of its internal parameters such as; RF gain, position update rate, tracking channel correlator spacing and code/carrier loop noise bandwidth. Correlator outputs, code/carrier error, Carrier-to-Noise Ratio (C/N0), navigation and RINEX data are provided to the end-user in real-time. This paper collectively highlights and reports on the implementation, test and validation of the novel techniques, elements and approaches in both the RF and digital part of the DCR that comprise the multi-constellation receiver.

The GNSS-R technique brings out the need for signal receiver systems to process both direct and reflected GNSS signals. This paper describes the architecture of a new GNSS-R receiver system (GRrSv.2) that features enhanced capabilities for remote sensing based on reflected Global Positioning System (GPS) signals. Signal processing issues including DDM calculation, Carrier and Code Generation and DDM Synchronization are presented. Aircraft- and land-based verification experiments for ocean winds, ocean Significant Wave Heights (SWH) and soil moisture have been performed and some primary results are presented in this paper.

A highly integrated transceiver microwave monolithic integrated circuit (MMIC) manufactured in a 200-GHz SiGe:C production technology is presented, applicable for sensing- and broadband communication applications. To simplify the analog frontend, the fully differential design is based on a homodyne architecture. It comprises an LO signal generation unit based on a wideband 60 GHz fundamental Voltage Controlled Oscillator (VCO) and an on-chip prescaler, covering the full operational frequency band of 57–64 GHz. Within this bandwidth, the upconverter exhibits an upconversion gain of 23.6–26.4 dB and a maximum output-referred 1-dB compression point of 14 dBm. The downconverter provides a Double Sideband (DSB) noise figure of 9–12 dB with a downconversion gain of 37–71 dB. On chip AC-coupling of the receiver IF-output with a lower −3 dB cut-off frequency as low as 16 kHz eliminates mixer DC-offsets and enables on-chip Intermediate Frequency (IF) amplification. The whole transceiver MMIC draws a current of 415 mA from a single 3.3 V supply and requires few components externally to the chip.

A fully integrated transmitter (TX) and receiver (RX) front-end chipset, produced in 0.25 µm SiGe:C bipolar and complementary metal oxide semiconductor (BiCMOS) technology, is presented. The front-end is intended for high-speed wireless communication in the unlicensed ISM band of 9 GHz around 60 GHz. The TXand RX features a modified heterodyne topology with a sliding intermediate frequency. The TX features a 12 GHz in-phase and quadrature (I/Q) mixer, an intermediate frequency (IF) amplifier, a phase-locked loop, a 60 GHz mixer, an image-rejection filter, and a power amplifier. The RX features a low-noise amplifier (LNA), a 60 GHz mixer, a phase-locked loop (PLL), and an IF demodulator. The measured 1-dB compression point at the TX output is 12.6 dBm and the saturated power is 16.2 dBm. The LNA has measured noise figure of 6.5 dB at 60 GHz. Error-free data transmission with a 16 quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal and data rate of 3.6 Gbit/s (without coding 4.8 Gbit/s) over 15 m was demonstrated. This is the best reported result regarding both the data rate and transmission distance in SiGe and CMOS without beamforming.

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

An effective linearization technique capable of equalizing IM3 products resulting from an arbitrary out-of-band blocking scenario in a wideband direct conversion receiver is presented. IM3 products are regenerated in the RF analog domain of a low-power mixed-signal feedforward path and are used to cancel analogous signal terms in the original receiver at digital baseband via adaptive equalization. The composite SAW-less receiver achieves an improvement in effective IIP3 from −7.1 to +5.3 dBm under worst-case UMTS Region 1 blocking when the feedforward path is active.