Practical Design Verification

Dhiraj K. Pradhan; Ian G. Harris

doi:10.1017/CBO9780511626913

Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT).

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Practical Design Verification

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Contents

Frontmatter
pp i-iv

Contents
pp v-ix

List of contributors
pp x-xii

1 - Model checking and equivalence checking
pp 1-50

2 - Transaction-level system modeling
pp 51-91

3 - Response checkers, monitors, and assertions
pp 92-112

4 - System debugging strategies
pp 113-121

5 - Test generation and coverage metrics
pp 122-153

6 - SystemVerilog and Vera in a verification flow
pp 154-172

7 - Decision diagrams for verification
pp 173-245

8 - Boolean satisfiability and EDA applications
pp 246-268

Index
pp 269-276

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