Article contents
A real-time on-chip network architecture for mixed criticality aerospace systems
Published online by Cambridge University Press: 13 August 2019
Abstract
Integrated Modular Avionics enables applications of different criticality levels to share the same hardware platform with an established temporal and spatial isolation. On-chip communication systems for such platforms must support different bandwidth and latency requirements of applications while preserving time predictability. In this paper, our concern is a time-predictable on-chip network architecture for targeting applications in mixed-criticality aerospace systems. The proposed architecture introduces a mixed, priority-based and time-division-multiplexed arbitration scheme to accommodate different bandwidth and latency in the same network while preserving worst-case time predictability for end-to-end communication without packet loss. Furthermore, as isolation of erroneous transmission by a faulty application is a key aspect of contingency management, the communication system should support isolation mechanisms to prevent interference. For this reason, a sampling port and isolated sampling buffer-based approach is proposed with a transmission authorisation control mechanism, guaranteeing spatial and temporal isolation between communicating systems.
Keywords
- Type
- Research Article
- Information
- Copyright
- © Royal Aeronautical Society 2019
Footnotes
This research is funded by Independent Research Foundation Denmark under grant number 6111-00363B.
References
REFERENCES
- 3
- Cited by