Ion Beam Etch for Patterning of Resistive RAM (ReRAM) Devices

Abstract

We investigate the feasibility of inert ion beam etch (IBE) for subtractive patterning of ReRAM-type structures. We report on the role of the angle-dependent ion beam etch rates in device area control and the minimization of sidewall re-deposition. The etch rates of key ReRAM materials are presented versus incidence angle and ion beam energy. As the ion beam voltage is increased, we demonstrate a significant enhancement in the relative etch rate at glancing incidence (for example, by a factor of 2 for HfO₂). Since the feature sidewall is typically exposed to glancing incidence, this energy-dependence plays a role in optimization of the feature shape and in sidewall re-deposition removal.

We present results of SRIM simulations to estimate depth of ion-bombardment damage to the TMO sidewall. Damage is minimized by minimizing ion energy; its depth can be reduced by roughly a factor of 5 over typical IBE energy ranges. For example, ion energies of less than ∼250 eV are indicated to maintain damage below ∼1nm. Multi-angle and multi-energy etch schemes are proposed to maximize sidewall angle and minimize damage, while eliminating re-deposition across the TMO. We utilize 2-D geometry/3-D etch model to simulate IBE patterning of tight-pitched ReRAM features, and generate etched feature shapes.