Hostname: page-component-cd9895bd7-8ctnn Total loading time: 0 Render date: 2024-12-28T03:10:48.715Z Has data issue: false hasContentIssue false
  • English
  • Français

Nanotopography Issues in Shallow Trench Isolation CMP

Published online by Cambridge University Press:  31 January 2011

Duane Boning  and
Brian Lee
Get access

Abstract

As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical–mechanical planarization (CMP). Previous work has shown that nanotopography—small surface-height variations of 10–100 nm in amplitude extending across millimeter-scale lateral distances on virgin wafers—can result in CMP-induced localized thinning of surface films such as the oxides or nitrides used in STI. A contact-wear CMP model can be employed to produce maps of regions on a given starting wafer that are prone to particular STI failures, such as the lack of complete clearing of the oxide in low spots and excessive erosion of nitride layers in high spots on the wafer. Stiffer CMP pads result in increased nitride thinning. A chip-scale pattern-dependent CMP simulation shows that substantial additional dishing and erosion occur because of the overpolishing time required due to nanotopography. Projections indicate that nanotopography height specifications will likely need to decrease in order to scale with smaller feature sizes in future IC technologies.

Keywords

chemical–mechanical planarizationchemical–mechanical polishingCMPcontact-wear simulationnanotopographyshallow trench isolation (STI)silicon wafers.
Type
Research Article
Information
MRS Bulletin , Volume 27 , Issue 10: Advances in Chemical-Mechanical Planarization , October 2002 , pp. 761 - 765
Copyright
Copyright © Materials Research Society 2002

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1.Ravi, K.V., Future Fab Int. 7 (1999) p. 207.Google Scholar
2.Xu, C.S., Zhao, E., Jairath, R., and Krussell, W., Electrochem. Solid-State Lett. 1 (4) (1998) p. 181.Google Scholar
3.Lee, B., Boning, D.S., Baylies, W., Poduje, N., Hester, P., Xia, Y., Valley, J., Koliopoulos, C., Hetherington, D., Sun, H., and Lacy, M., in Chemical–Mechanical Polishing 2001—Advances and Future Challenges, edited by Babu, S.V., Cadien, K.C., and Yano, H. (Mater. Res. Soc. Symp. Proc. 671, Warrendale, PA, 2001) p. M4.9.1.Google Scholar
4.Park, J.-G., Katoh, T., Yoo, H.C., and Park, J.-H., Jpn. J. Appl. Phys., Part 2: Lett. 40 (2001) p. L857.CrossRefGoogle Scholar
5.Schmolke, R., Deters, R., Thieme, P., Pech, R., Schwenk, H., and Diakourakis, G., J. Electrochem. Soc. 149 (4) (2002) p. G257.CrossRefGoogle Scholar
6.Lee, B., Boning, D.S., Baylies, W., Poduje, N., and Valley, J., “Modeling and Mapping of Nanotopography Interactions with CMP,” presented at Symposium I, Materials Research Society Meeting, San Francisco, April 2002, paper No. I1.5.CrossRefGoogle Scholar
7.Chekina, O.G. and Keer, L.M., J. Electrochem. Soc. 145 (6) (1998) p. 2100.CrossRefGoogle Scholar
8.Yoshida, T., in Proc. 3rd Int. Symp. on Chemical– Mechanical Planarization in IC Device Manufacturing, Vol. 99–37 (The Electrochemical Society, Pennington, NJ, 1999) p. 593.Google Scholar
9.Ouma, D., Boning, D., Chung, J., Shinn, G., Olsen, L., and Clark, J., in Proc. Int. Interconnect Technology Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 1998) p. 67.Google Scholar
10.Boning, D., Lee, B., Baylies, W., Poduje, N., and Valley, J., “Impact of Nanotopography on STI CMP in Future Technologies,” presented at the Workshop on Metrology for Silicon Wafers for 100-nm Technology Generations and Beyond, SEMI/Europa, Munich, April 2002.Google Scholar
11.Shum, D.P., Higman, J.M., Khazhinsky, M.G., Wu, K.Y., Kao, S., Burnett, J.D., and Swift, C.T., in IEDM Tech. Dig. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 1997) p. 665.Google Scholar
12.Pan, J.T., Ouma, D., Li, P., Boning, D., Redecker, F., Chung, J., and Whitby, J., “Planarization and Integration of Shallow Trench Isolation,” presented at the VLSI Multilevel Interconnect Conf., Santa Clara, CA, June 1998.Google Scholar
13.Lee, B., PhD thesis, Massachusetts Institute of Technology, May 2002.Google Scholar