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Scaling computation with silicon photonics

Published online by Cambridge University Press:  14 August 2014

Lionel C. Kimerling ,
Dim-Lee Kwong  and
Kazumi Wada
Lionel C. Kimerling
Affiliation:
MIT Microphotonics Center, Massachusetts Institute of Technology, USA; lckim@mit.edu
Dim-Lee Kwong
Affiliation:
Institute of Microelectronics, Agency for Science, Technology and Research, Singapore; kwongdl@ime.a-star.edu.sg
Kazumi Wada
Affiliation:
Department of Materials Engineering; University of Tokyo, Japan; kwada@material.t.u-tokyo.ac.jp
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Abstract

Fundamental latency and energy limitations are driving major changes in communication and computation hardware. Parallel multicore and multiprocessor architectures are emerging as highly interconnected, communication-centric computation tools that at high node count will approach neural network connectivity and complexity. Monolithically integrated silicon photonics with electronics offers a promising platform for scaling functionality with high volume manufacturing and short design cycle times. The system parameters for this emerging “design for function” paradigm are cost, energy, and bandwidth density. The platform has been built on transmission of a λ ≈ 1550 nm photon wavelength; Si, Ge, Si3N4, and SiO2 materials; and standard complementary metal oxide semiconductor foundry processing. Dimensional shrink is achieved through strong signal confinement in high refractive index contrast material composites. Precision pattern transfer has enabled both photonic interconnect and signal processing functionality. New materials, process integration, and packaging are the keys to success.

Keywords

SiGedislocationsoptoelectroniclaserpackagingdiffusionCVD (deposition)epitaxy
Type
Research Article
Information
MRS Bulletin , Volume 39 , Issue 8: New Materials for Post-Si Computing , August 2014 , pp. 687 - 695
Copyright
Copyright © Materials Research Society 2014 

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