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A 3D Soft-EHL Model for Simulating Feature-scale Defects in Advanced Node ICs

Published online by Cambridge University Press:  10 July 2013

Jonatan A. Sierra-Suarez ,
Gagan Srivastava  and
C. Fred Higgs
Jonatan A. Sierra-Suarez
Affiliation:
Electrical and Computer Engineering Department Carnegie Mellon University, Pittsburgh, PA 15232, U.S.A.
Gagan Srivastava
Affiliation:
Mechanical Engineering Department Carnegie Mellon University, Pittsburgh, PA 15232, U.S.A.
C. Fred Higgs
Affiliation:
Electrical and Computer Engineering Department Carnegie Mellon University, Pittsburgh, PA 15232, U.S.A. Mechanical Engineering Department Carnegie Mellon University, Pittsburgh, PA 15232, U.S.A.
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Abstract

A new multiphysics, multiscale framework is presented which is capable of capturing and predicting both wafer-scale and feature-scale defects. Through physics-based modeling, the empirical wear/Preston coefficient often found in popular feature scale models has been eliminated. Simulation results show the topography evolution of an actual metal 1 layout between two dies located in different positions on a wafer during the CMP process.

Keywords

simulationnanoscaleCMP
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1560: Symposium BB – Evolutions in Planarization—Equipment, Materials, Techniques and Applications , 2013 , mrss13-1560-bb02-02
Copyright
Copyright © Materials Research Society 2013 

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References

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