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Buried Oxide Soi: Materials, Devices, and VLSI Circuits

Published online by Cambridge University Press:  28 February 2011

C.-E. Daniel Chen  and
Rad-Hard Soi Project Team
C.-E. Daniel Chen
Affiliation:
Semiconductor Process and Design Center, Texas Instruments, Inc. MS 944, P. O. Box 655621, Dallas,TX 75265.
Rad-Hard Soi Project Team
Affiliation:
Semiconductor Process and Design Center, Texas Instruments, Inc. MS 944, P. O. Box 655621, Dallas,TX 75265.
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Abstract

In the past couple of years, buried oxide SOI has emerged as the leading SOI approach. Significant advances have been made in the understanding and the preparation of the buried oxide substrates. Various VLSI circuits have been demonstrated with excellent results, proving the maturity and the manufacturability of this technology. In this paper, buried oxide material properties, device parameters and the implementation of a 2.5 urn 4K SRAM and a 1.25 pm 16K SRAM on the buried oxide substrates are reviewed.

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 107: Symposium H – Silicon-on-Insulator and Buried Metals in Semiconductors , 1987 , 309
Copyright
Copyright © Materials Research Society 1988

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References

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