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Published online by Cambridge University Press: 22 February 2011
The properties of polycrystalline silicon layers deposited by RTCVD have been studied by texture, stress and electrical analyse. The intrinsic layers intended for applications in integrated IC processing are very much textured with the preferred orientation depending on deposition temperature and atmosphere. Very low residual film stress in the order of 10 dyn/cm2 was detected, and a transition from compressive to tensile stress with increasing deposition temperature around 800°C was observed. This was associated with the development of the columnar structure by the (110) orientation becoming dominant at the expense of the (100) texture. Also the effect of post-deposition anneal ambience on the grain structure has been studied. Grain size and grain-boundary trapping in after doped layers have been evaluated in P-implanted RTA activated layers.