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A Dimple-Array Interconnect Technique for Power Semiconductor Devices

Published online by Cambridge University Press:  21 March 2011

Simon S. Wen
Affiliation:
Power Electronics Packaging Laboratory, Center for Power Electronics Systems, The Bradley Department of Electrical and Computer Engineering, Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA, Phone: 1-540-231-3233, Email: swen@vt.edu
Daniel Huff
Affiliation:
Power Electronics Packaging Laboratory, Center for Power Electronics Systems, The Bradley Department of Electrical and Computer Engineering, Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA, Phone: 1-540-231-3233
Guo-Quan Lu
Affiliation:
Power Electronics Packaging Laboratory, Center for Power Electronics Systems, The Bradley Department of Electrical and Computer Engineering, Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA, Phone: 1-540-231-3233
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Abstract

This paper describes a wireless-bond interconnect technique, termed Dimple-Array Interconnect (DAI) technique for packaging power devices. Electrical connections onto the devices are established by soldering arrays of dimples pre-formed on a metal sheet. Preliminary experimental and analytical results demonstrated potential advantages of this technique such as reduced parasitic noises, improved heat dissipation, as well as lowered processing complexity, compared to the conventional wire bonding technology in power module manufacturing. Thermomechanical analysis using thermal cycling test and FEM were also performed to evaluate the reliability characteristics of this interconnect technique for power devices.

Type
Research Article
Copyright
Copyright © Materials Research Society 2001

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References

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