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High Temperature off Current in a-Si TFTS - Effect of Process and Structure

Published online by Cambridge University Press:  21 February 2011

George E. Possin
George E. Possin*
Affiliation:
General Electric Corp. Res. and Dev, P. O.Box 8, Schenectady, NY 12301
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Abstract

The OFF current in a-Si TFTs is an important parameter, especially for applications such as active matrix liquid crystal displays. In some demanding applications operation at 70°C or higher is required. This paper reports studies of the OFF current limiting mechanisms at room temperature and above. It is shown that the limiting mechanisms are hole injection from the drain junction at room temperature and electron conduction at higher temperatures. The importance of silicon thickness and interface state density at the passivation interface is stressed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 219: Symposium A – Amorphous Silicon Technology - 1991 , 1991 , 327
Copyright
Copyright © Materials Research Society 1991

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References

REFERENCES

1) Powell, M. J. IEEE Trans ED 36 #12,.2753 (1989).CrossRefGoogle Scholar
2) Possin, G. E. & Su, F. C., Mater. Res. Soc. Symp. Proc. 118, 255 (1988).CrossRefGoogle Scholar
3) Powell, M. J. & Pritchard, J., J. Appl. Phys, 54, 3244 (1983).CrossRefGoogle Scholar
4) Spear, W. E. & LeComber, P. G., Philos. Mag. (GB) 33, 935 (1976).CrossRefGoogle Scholar