No CrossRef data available.
Published online by Cambridge University Press: 01 February 2011
We have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤ 700 °C), we have demonstrated elevated source/drain formation on ultra-thin (< 50 Å) body SOI transistors without Si agglomeration, smooth morphology of selective SiGe epitaxy with high [Ge] (>30 %) and [B] (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.