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A Novel Bi-Layer Photoresist T-Gate Technique To Reduce Gate Resistance.

Published online by Cambridge University Press:  10 February 2011

J. R. Lothian  and
F. Ren
J. R. Lothian
Affiliation:
Bell-Labs, Lucent Technologies, Murray Hill, N. J.
F. Ren
Affiliation:
Bell-Labs, Lucent Technologies, Murray Hill, N. J.
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Abstract

As the gate dimensions of FET's continue to shrink, the gate resistance increases. This increased gate resistance is undesirable for power applications. In order to reduce this problem short gate length features are covered with a larger length feature to reduce the gate resistance (T-gate)1. Generally this is done using bi-layer PMMA and E-beam writing for the upper and lower features, but this technique is very expensive and time consuming2,3. It is desirable to find a technique using conventional photoresist that would replace e-beam to produce T-gates.

We demonstrate a novel technique that utilizes conventional photoresist and optical stepper to create T-gate features4. The bottom feature is exposed and developed creating the lower part of the T. A short exposure of the photoresist pattern to an argon plasma hardens the resist just enough to allow a second layer to be put on without mixing of the two layers. This second layer is then exposed and developed forming the T. Plasma exposure allows us to create the second resist layer pattern without distorting or changing the bottom layer pattern. This technique is very robust, fast and much cheaper than e-beam technology.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 483: Symposium E – Power Semiconductor Materials & Devices , 1997 , 271
Copyright
Copyright © Materials Research Society 1998

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References

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