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Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

Published online by Cambridge University Press:  10 February 2011

Vijay Parihar  and
R. Singh
Vijay Parihar
Affiliation:
Center for Silicon Nanoelectronics, Department of Electrical and Computer Engineering, Clemson University, Clemson, SC, 29634-0915
R. Singh
Affiliation:
Center for Silicon Nanoelectronics, Department of Electrical and Computer Engineering, Clemson University, Clemson, SC, 29634-0915, raj.singh@ces.clemson.edu
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Abstract

The continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 511: Symposium E – Low Dielectric Constant Materials IV , 1998 , 241
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

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