Resolving the Origin of a Cmp-Associated Yield/Reliability Issue “Center Spike”– Film Thickness Bulge in the Wafer Center. is CMP to Be Held Responsible for Its Appearance?

Abstract

A long-standing CMP related yield/reliability puzzle - film thickness spike, frequently appearing at the wafer center after it is processed by CMP, was studied. Optical film thickness measurements for pre- and post-CMP film were compared with surface topography profiles. Wafer surface profiles were also studied after the oxide film was HF-etched out. It was found that the post-CMP film thickness spike actually is not caused by CMP malfunctioning, but originates to a specific bare silicon wafer defect and occurs when the bare silicon wafer has a narrow dip-like defect (depression) in its center. The dielectric film, deposited over the wafer, follows the underlying center-dipped topography, and, being planarized by CMP, is transformed into a top-flat film with a thick pattern in the wafer center, filling the silicon dip. In-line and end-of-line yield related issues are discussed.