Analysis and Suppression of Process-Induced Defects in Memory Devices.

Abstract

In this paper we show that dopant decoration of process-induced defects is responsible for a failure mechanism of memory devices. From the electrical point-of-view, the defect-related failure consists in a source-to-drain resistive path formed by junction piping. This mechanism is made active by the very close spacing which is typical of present device structures. A device-like test structure is used for defect detection. This structure proves to be a very effective tool for studying the impact of various process steps on defect generation, in that it allowes statistical data about the formation of these defects to be collected. TEM analyses are extensively used for studying the evolution of end-of-range defects during subsequent thermal treatments and for measuring the amorphous layer width under various implantation conditions.

The role of high dose implantations in the generation of this sort of defects is discussed. Even if the amorphous layer is completely recovered by a suitable recristallization annealing, residual defects grow and become dopant-decorated during post-implantation thermal treatments. Defect density is increased by oxidizing treatments. In this case point defect injection is active both in enhancing dopant diffusion and in growing defects.

Defect formation is suppressed if the amorphous layer is made very shallow (≤ 50 nm) by suitable choices of the screen oxide and of the implantation energy. A binary collision code is used in order to estimate the dependence on energy of the self-interstitial excess outside the amorphous region. The results of these calculations indicate that defect suppression can be tentatively explained by point defect annihilation at the silicon surface.