Hostname: page-component-cd9895bd7-jkksz Total loading time: 0 Render date: 2024-12-30T23:04:20.519Z Has data issue: false hasContentIssue false
  • English
  • Français

The Development of a Direct-Polish Process for STI CMP

Published online by Cambridge University Press:  01 February 2011

Antonella Martin ,
Giulia Spinolo ,
Sonia Morin ,
Maurizio Bacchetta ,
Francesca Frigerio ,
Benjamin A. Bonner ,
Peter McKeever ,
Maurizio Tremolada  and
Anand Iyer
Antonella Martin
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Giulia Spinolo
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Sonia Morin
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Maurizio Bacchetta
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Francesca Frigerio
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Benjamin A. Bonner
Affiliation:
Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA
Peter McKeever
Affiliation:
Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA
Maurizio Tremolada
Affiliation:
Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA
Anand Iyer
Affiliation:
Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA
Get access

Abstract

The development of a direct polish process for STI CMP on 200mm wafers using highselectivity slurry (HSS) has been achieved for production of 0.13μm technology microelectronic devices. The new process has improved on-wafer performance compared to standard STI CMP processes. The step height range across the wafer was decreased by 84%, planarity Cpk values (silicon nitride thickness and step-height uniformity) were increased by >25%, leakage current statistics were superior, and the cost of ownership was lowered by 78%. Cross-sectional SEMs both after direct polish CMP and after removal of the silicon nitride show improved planarity.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 767: Symposium F – Chemical-Mechanical Planarization , 2003 , F5.10
Copyright
Copyright © Materials Research Society 2003

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Steigerwald, J. M., Murarka, S. P., and Gutmann, R. J., Chemical Mechanical Planarization of Electronic Materials (Wiley-Interscience, New York, 1996), p. 273.Google Scholar
2. Withers, B., Zaho, E. Krusell, W. Jairath, R. and Hosali, S., Solid State Technol., July (1998), p. 173.Google Scholar
3. Zhao, E. and Xu, C. S., Semiconductor International, 145 (2001).Google Scholar
4. Morrison, W. Hunt, K. Olsen, L., Strupp, J. Sees, J. and Misra, A. in VMIC Conference, Sept. 7-9, (1999), p. 217.Google Scholar
5. Gan, T. Tugbawa, T. Lee, B. Boning, D. S., and Jang, S. J. Electrochem. Soc., 148, G159 (2001).Google Scholar
6. Boyd, J. M. and Ellul, J. P., J. Electrochem. Soc., 144, 1838, (1997).Google Scholar
7. Bonner, B. A., Iyer, A. Kumar, D. Zhang, B. Osterheld, T. H., and Nickles, A. S., in Proceedings Seventh International CMP-MIC Conference at Santa Clara, CA Feb 27-Mar 1, (2002), p. 247.Google Scholar
8. Schiltz, A. Palatini, L. Paoli, M. Rivoire, M. and Prola, A. J. Vac. Sci. Technol., A 18 (4) (2000), p. 1313.Google Scholar
9. Buley, T. Gagliardi, J. Funkenbusch, E. in Proceeings Sixth International CMP-MIC Conference at Santa Clara, CA Mar 7-8, (2001), p. 535.Google Scholar