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Electrical Test Sites for AMLCD-TFT Array Process Characterization

Published online by Cambridge University Press:  10 February 2011

E.G. Colgan ,
R.J. Polastre ,
M. Takeichi  and
R. L. Wisnieff
E.G. Colgan
Affiliation:
IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, ecolgan@ibm.us.com
R.J. Polastre
Affiliation:
IBM T.J. Watson Research Center, Yorktown Heights, NY 10598
M. Takeichi
Affiliation:
TFT Array Process Engineering, IBM Japan, Yasu, Japan
R. L. Wisnieff
Affiliation:
IBM T.J. Watson Research Center, Yorktown Heights, NY 10598
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Abstract

Electrical test structures provide a method of rapid and low cost end-of-process metrology for both materials properties and specific process information. We have demonstrated the use of electrical test structures for monitoring key process parameters such as line width, edge taper width, layer-to-layer alignment, and data metal coverage over topography. These results are compared with those from traditional metrology methods and in all cases, the correlation was good, demonstrating that electrical test structures have sufficient accuracy for process control applications. For the structures used, the line width, edge taper width, and layer-to-layer alignment electrical measurements have uncertainties of less than 0.1 micron. A novel capacitance method was used for layer-to-layer alignment measurements and a combination of resistive and capacitive line width measurements were used to electrically determine the gate metal taper width. The test structures are all compatible with typical thin film transistor array processing.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 508: Symposium B – Flat Panel Display Materials - 1998 , January 1998 , 79
Copyright
Copyright © Materials Research Society 1998

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