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Electronic Transport Properties of Cu/MnOx/SiO2/p-Si MOS Devices

Published online by Cambridge University Press:  31 January 2011

Vijay Kumar Dixit ,
Koji Neishi  and
Junichi Koike
Vijay Kumar Dixit
Affiliation:
dixit@material.tohoku.ac.jpdixit@rrcat.gov.in, Tohoku University, Material Science and Engineering, Sendai, Japan, Sendai, Miyagi, 980-8579, Japan
Koji Neishi
Affiliation:
neishi@material.tohoku.ac.jp, Tohoku University, Material Sciences, Sendai, Japan
Junichi Koike
Affiliation:
koikej@material.tohoku.ac.jp, Tohoku Universuty, Sendai, Japan
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Abstract

An ultrathin barrier layer of MnOx was grown using metal organic chemical vapor deposition (MOCVD) at an interface between Cu and SiO2 dielectric. The electronic transport properties of Cu/MnOx/SiO2/p-Si metal oxide semiconductor (MOS) devices showed leakage current density within the range of 10-8-10-7A/cm2 up to an electric field of 4MV/cm. The current density remained within the same range after bias temperature aging test at 3MV/cm for 6×103s at 550K. The capacitance-voltage curves of the MOS device having the MnOx layer grown at 473K do not show significant shift of flat band voltage after thermal annealing at 673K for 3.6×103s as well as after bias temperature aging test at 1MV/cm, 550K for 2.4×103 s. These results indicate that the ultrathin layer of MnOx is stable under the above conditions and prevents sufficiently Cu ion diffusion into the SiO2 dielectric.

Keywords

amorphouschemical vapor deposition (CVD) (deposition)Cu
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1156: Symposium D – Materials, Processes and Reliability for Advanced Interconnects for Micro-and Nanoelectronics–2009 , 2009 , 1156-D04-11
Copyright
Copyright © Materials Research Society 2009

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References

1 Murarka, P. Metallization - Theory and Practice for VLSI-ULSI (Butterworth-Heineman, Boston, 1993).Google Scholar
2International Technology Roadmap for Semiconductors, Semiconductor Industry Association (2003).Google Scholar
3 Neishi, K. Aki, S. Matsumoto, K. Sato, H. Itoh, H. Hosaka, S. and Koike, J. Appl. Phys. Lett., 93, 032106, (2008).Google Scholar
4 Dixit, V. K. Neishi, K. Akao, N. and Koike, J. (Unpublished).Google Scholar
5 Murarka, S.P. Verner, I. V. Gutmann, R. J. Copper - fundamental mechanisms for microelectronic applications, (Wiley, New York, 2000).Google Scholar
6 Usui, Takamasa, Nasu, Hayato, Takahashi, Shingo, Shimizu, Noriyoshi, Nishikawa, T. Yoshimaru, Masaki, Shibata, Hideki, Wada, Makoto, and Koike, Junichi. IEEE Transactions on Electron Devices, 53, 2492, (2006).Google Scholar
7 Felipe, T. Suwwan de, Ph. D Thesis, Rensselaer Polytechnic Institute, Troy, NY, (1998).Google Scholar
8 Felipe, T. Suwwan de, Murarka, S. P. Bedell, S. and Lanford, W. A. J. Vac. Sci. Technol. B, 15, 1987 (1997).Google Scholar