Hostname: page-component-78c5997874-s2hrs Total loading time: 0 Render date: 2024-11-13T02:19:57.515Z Has data issue: false hasContentIssue false
  • English
  • Français

Evaluation of Void Formation Mechanism in Cu Thin Films; Separation of The Effect of Electron Wind Force and Stress

Published online by Cambridge University Press:  26 February 2011

Yousuke Fujii ,
Masanori Tsutsumi ,
Junya Inoue  and
Toshihiko Koseki
Yousuke Fujii
Affiliation:
fujii@metall.t.u-tokyo.ac.jp, The University of Tokyo, Materials Engneering, Hongo 7-3-1, Bunkyo, Tokyo, 113-8656, Japan, 03-5841-7165
Masanori Tsutsumi
Affiliation:
masa.tsutsumi@jp.fujitsu.com, Fujitsu Co.Ltd., 50 Fuchigami, Tokyo, 197-0833, Japan
Junya Inoue
Affiliation:
inoue@material.t.u-tokyo.ac.jp, The University of Tokyo, Department of Materials Engneering, 7-3-1 Hongo, Bunkyo, Tokyo, 113-8656, Japan
Toshihiko Koseki
Affiliation:
koseki@material.t.u-tokyo.ac.jp, The University of Tokyo, Department of Materials Engneering, 7-3-1 Hongo, Bunkyo, Tokyo, 113-8656, Japan
Get access

Abstract

Electromigration (EM) and stress-induced voiding (SIV) in Cu and Cu alloys thin films were studied separately. The characterization of EM was evaluated in a modified interconnect structure where the effect of current density can be observed in the absence of stress disturbance. SIV, on the other hand, is examined in detail by applying a uniform stress to Cu films without electric current. Results of EM tests clearly showed that void and hillock formations were concentrated mainly in the region with high current density gradient without stress disturbance. SIV test performed under the high stress of 1GPa showed that voids were observed to form at grain boundaries and grain boundary triple junctions. Under the high stress, SIV is shown to be generated in the absence of stress gradient. Also, the effect of alloying to EM and SIV was investigated in detail.

Keywords

Cuelectromigrationnanostructure
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 968: Symposium V – Advanced Electronic Packaging , 2006 , 0968-V05-07
Copyright
Copyright © Materials Research Society 2007

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. ITRS: The International Roadmap for Semiconductors 2005 EditionGoogle Scholar
2. Padhi, D. et al.: Journal of Applied Physics, 94, 10 (2003), 6463–6467 Google Scholar
3. Vairagar, A.V. et al.: Microelectronics Reliability 44 (2004), 747–754 Google Scholar
4. Ogawa, E.T. et al.: IEEE International Reliability Physics Symposium. Proc. 40th Annual, 2002, p 312–21Google Scholar
5. Glasow, A. von et al.: Proc. IEEE 2002 Int. Interconnect Technology Conference, (2002), 274–276 Google Scholar
6. Hummel, R.E: International Material Reviews, 39, 3 (1994), 97–111 Google Scholar
7. Clement, J.J. et al.: Journal of Applied Physics, 78, 2 (1995), 900–904 Google Scholar
8. Hau-Riege, C.S. et al.: Applied Physics Letter, 78, 22 (2001), 3451–3454 Google Scholar
9. Kumakawa, et al.: Japan Journal of Applied Physics, 31 (1992), L1147–L1149Google Scholar
10. Giroux, F. et al.: Proc. IEEE 1995 Int. Conf. on Microelectronic Test Structure, 8, (1995), 229–232 Google Scholar