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Evidence of Ti-related Inclusions in an Al Alloy Interconnecting Layer for Nanometer 256MBit DRAM Semiconductor Devices Characterized by TEM, STEM, EELS Elemental Mapping, and XEDS Linescan

Published online by Cambridge University Press:  11 February 2011

Wei Zhao
Affiliation:
Department of Technology Transfer, Infineon Technologies Richmond 6000 Technology Blvd., Sandston, VA 23150, USA
Steve Graca
Affiliation:
Department of Technology Transfer, Infineon Technologies Richmond 6000 Technology Blvd., Sandston, VA 23150, USA
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Abstract

With the introduction of high aspect ratio and steep geometries in deep-subquarter-micron dynamic random access memory (DRAM) device, it becomes more and more critical to understand the formation of undesired intermetallic Ti-Al phases in Al-metallization and thus better-control the profile of interconnectors. In this article, Ti-related inclusions in Metal 1 (M1) interconnecting layer (an AlCu-0.5% alloy) originated from the bottom Ti liner were characterized with an Analytical TEM. Samples were cleaved from nanometer 256Mbit dynamic random access memory DRAM devices. The TEM employed is a JEOL 2010F with a field emission gun (FEG) and running at 200KV acceleration voltage. Correlations among transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), electron energy loss spectroscopy (EELS) elemental mapping, and x-ray energy dispersive spectroscopy (XEDS) elemental linescan were established. The results here not only provide important feedbacks to semiconductor product integration and optimization, but also demonstrate the full-functionality of the start-of-the-art analytical TEM in investigations of nanometer semiconductor devices.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

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References

REFERENCES

Sze, S. M., Semiconductor Devices - Physics and Technology, (John Wiley & Sons, New York, 1985) pp. 364∼380.Google Scholar
2. Wolf, S., Silicon Processing for The VLSI Era - Process Technology, 2nd ed. (Lattice Press, Sunset Beach, CA, 2000) pp. 434∼487Google Scholar
3. Zhao, W. and Luzzi, D. E. in Influences of Interface and Dislocation Behavior on Microstructure Evolution, edited by Aindow, M., Asta, M. D., Glazov, M. V., Medlin, D. L., Rollett, A. D., and Zaiser, M. (Mater Res Soc Proc 652, Boston MA, 2000) pp.Y10.4.1∼6.Google Scholar
4. Zhao, W., to be presented at Symposium G: Spatially Resolved Characterization of Local Phenomena in Materials and Nanostructures, MRS 2002 Fall Meeting.Google Scholar
5. Zhao, W., Liaw, P. K., Belardinelli, R., Joy, D. C.; Brooks, C. R., McHargue, C. J., Metallurgical and Materials Transactions A, 31 (3A), 911920 (2000)Google Scholar
6. Zhao, W., Liaw, P. K. and Joy, D. C., Ceramic Engineering and Science Proceedings, 18 (3), 295302 (1997)Google Scholar
7. Zhao, W., Liaw, P. K., Joy, D. C. and Brooks, C. R., Processing and Properties of Advanced Materials: Modeling, Design and Properties, edited by Li, B. Q., (The Minerals, Metals, and Materials Society, 1998) pp. 283294.Google Scholar
8. Zhao, W., Liaw, P. K. and Joy, D. C., JOM, 48 (11), 142 (1996).Google Scholar
9. Zhao, W., Liaw, P. K., Joy, D. C., et al., Ceramic Bulletin, 75 (12), 102, (1996)Google Scholar