Published online by Cambridge University Press: 10 February 2011
Passivation of the SiO2-Si interface by hydrogen/deuterium in MOS transistors serve to ensure their operating reliability against channel hot carriers. Physical characterization of device sintering process in deuterated forming gas (10%D2:90%N2) is carried out by dynamic SIMS on planar CMOS gate stack structures, in conjunction with device hot carrier electrical testing. It is found that incorporation of deuterium in the doped poly-Si/SiO2/Si interfacial region readily occurs under typical post-metallization sintering conditions, demonstrating that transport of deuterium through CMOS gate is an effective pathway in an encapsulated device structure with silicon nitride sidewalls. The measured Si-D areal densities in the interfacial region depend on gate poly-Si doping type, but in both cases, appear to be sufficient to achieve complete interface Si dangling bond (˜1012 cm−2) passivation for the SiO2-Si system.