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Integration Challenges for Double-Gate MOSFET Technologies

Published online by Cambridge University Press:  15 March 2011

W.P. Maszara
W.P. Maszara*
Affiliation:
Strategic Technology Group, Advanced Micro Devices Sunnyvale, CA 94088-3453
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Abstract

Device modeling data and some early experiments suggests that fully depleted MOSFET devices where channel is controlled by two opposing gates or one gate that surrounds most or the entire channel, will provide better scaling than the classic devices with one gate on one side of the channel. However, formation of such devices requires complex, non-conventional and sometimes exotic geometry and processing, ranging from wafer bonding to selective lateral ‘tunnel’ epitaxy, to selectively wet-etched channels with triangular cross-section. Classic single-gate transistors have been recently demonstrated with reasonable performance at 20-15 nm of physical gate length. Double-gate transistors with their process integration complexity will likely become a viable alternative for smaller geometries. This paper will discuss various approaches to realization of those multi-gate fully depleted devices and their process integration challenges for sub-15 nm gates.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 686: Symposium A – Materials Issues in Novel Si-Based Technology , 2001 , A2.5
Copyright
Copyright © Materials Research Society 2002

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References

1. “International Technology Roadmap for Semiconductors”, by SIA and SEMATECH, 2001.Google Scholar
2. Yu, B. et al. , VLSI Technology Tech.Dig., p. 9, 2001.Google Scholar
3. Inaba, S. et al. , IEDM Tech.Dig., 2001.Google Scholar
4. Narasimha, S. et al. , IEDM Tech.Dig., 2001.Google Scholar
5. Chau, R., Silicon Nanoelectronics Workshop Abstracts, p. 2, 2001.Google Scholar
6. Yu, B. et al. , IEDM Tech.Dig., 2001.Google Scholar
7. Boeuf, F. et al. , IEDM Tech.Dig., 2001.Google Scholar
8. Taur, Y. et al. , IEEE Proc., p. 486, 1997.Google Scholar
9. Huang, X. et al. , IEDM Tech.Dig., p. 67, 1999.Google Scholar
10. Choi, Y.-K. et al. , IEDM Tech. Dig., 2001.Google Scholar
11. Kedzierski, J. et al. , IEDM Tech.Dig., 2001.Google Scholar
12. Ballestra, F. et al. , IEEE EDL, p.410, 1987.Google Scholar
13. Colinge, J.-P. et al. , IEDM Tech.Dig. p. 595, 1990.Google Scholar
14. Esseni, D. et al. , IEDM Tech.Dig., 2001.Google Scholar
15. Park, J.-T. et al. , IEEE International SOI Conf.Proc., p.115, 2001.Google Scholar
16. Wong, H.-S. et al. , IEDM Tech.Dig., p. 747, 1994.Google Scholar
17. Hisamoto, D. et al. IEDM Tech.Dig., p. 833, 1989.Google Scholar
18. Hisamoto, D. et al. IEDM Tech.Dig., p. 1032, 1998.Google Scholar
19. Takagi, S. et al. , IEEE Trans. Electron Dev., 41, p. 2363, 1994.Google Scholar
20. Saito, T. et al. , Silicon Nanoelectronics Workshop Abstracts, p. 6, 2001.Google Scholar
21. Takato, H. et al. , IEDM Tech.Dig., p. 222, 1988.Google Scholar
22. Gossner, H. et al. , Electron Lett., 31, p. 1394, 1995.Google Scholar
23. Auth, C.P. and Plummer, J.D., 54th Annual Dev.Res.Conf.Tech.Dig., p. 108, 1996.Google Scholar
24. Klaes, D. et al. , Thin Solid Films, 336, p. 306, 1998.Google Scholar
25. Hergenrother, J.M. et al. , IEDM Tech.Dig., p. 75, 1999.Google Scholar
26. Hergenrother, J.M. et al. , IEDMTech.Dig., 2001.Google Scholar
27. Oh, S.-H.et al, IEDM Tech.Dig., p. 65, 2000.Google Scholar
28. Monroe, D. & Hergenrother, J.M., ISSCC Tech.Dig., p. 134, 2000.Google Scholar
29. Wong, H.-S. et al. , IEDM Tech.Dig., p. 427, 1997.Google Scholar
30. Neudeck, G.W. et al. , IEDM Tech.Dig., p.169, 2000.Google Scholar
31. Guarini, K.W. et al. , IEDM Tech.Dig., 2001.Google Scholar