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Interconnect Technologies for Heterogeneous 3D Integration : CMOS and MEMS

Published online by Cambridge University Press:  01 February 2011

Hyung Suk Yang
Affiliation:
jyang@gatech.edu, Georgia Institute of Technology, Nanotechnology Research Center, Atlanta, United States
Muhannad Bakir
Affiliation:
muhannad.bakir@mirc.gatech.edu, Georgia Institute of Technology, Nanotechnology Research Center, Atlanta, Georgia, United States
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Abstract

Microelectromechanical Systems (MEMS) market is a rapidly growing market with a wide range of devices. Most of these devices require an interaction with an electronic circuit, and with the increasing number of high performance MEMS devices that are being introduced, a demand for integrating CMOS and MEMS using high-density and low-parasitic interconnects have also been on the rise.

Unfortunately, conventional methods of integrating CMOS with MEMS cannot provide the high density and low-parasitic interconnections required by modern high performance MEMS devices, and at the same time provide the flexibility required to accommodate new devices that are made using new materials and highly innovative fabrication processes.

Heterogeneous 3D integration of MEMS and CMOS has the potential to provide both the performance and the integration flexibility; however there are two interconnect challenges that need to be addressed. This paper outlines the details of these interconnect challenges and introduces two interconnect technologies, Mechanically Flexible Interconnects (MFI) and Through-Silicon Via (TSV), developed specifically to address these challenges.

Type
Research Article
Copyright
Copyright © Materials Research Society 2010

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References

1 Mounier, E., Robin, L., and Mouly, J., Emerging MEMS: Technologies & Markets, 2010 Report, Lyon, France: Yole, 2010.Google Scholar
2 Witvrouw, A., Steenkiste, F. Van, Maes, D., Haspeslagh, L., Gerwen, P. Van, Moor, P. De, Sedky, S., Hoof, C. Van, Vries, A.C. de, Verbist, A., Caussemaeker, A. De, Parmentier, B., and Baert, K., “Why CMOS-integrated transducers? A review,” Microsystem Technologies, vol. 6, 2000, pp. 192199.Google Scholar
3IC & MEMS Integration Abstract, Yole Development, 2004 Google Scholar
4 Baltes, H., Brand, O., Fedder, G.K., Hierold, C., Korvink, J.G., and Tabata, O., CMOSMEMS: Advanced Micro and Nanosystems, Wiley-VCH, 2005.Google Scholar
5 Lishchynska, M., O'Mahony, C., Slattery, O., Wittler, O., and Walter, H., “Evaluation of Packaging Effect on MEMS Performance: Simulation and Experimental Study,” IEEE Transactions on Advanced Packaging, vol. 30, 2007, pp. 629635.Google Scholar
6 Pustan, D., Rastiagaev, E., and Wilde, J., “In situ analysis of the stress development during fabrication processes of micro-assemblies,” Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 117124.Google Scholar
7 Rahim, M., Suhling, J., Copeland, D., Islam, M., Jaeger, R., Lall, P., and Johnson, R., “Die stress characterization in flip chip on laminate assemblies,” Components and Packaging Technologies, IEEE Transactions on, vol. 28, 2005, pp. 415429.Google Scholar
8 Chow, E. M., Bruyker, D. De, Shubin, I., Cunningham, J., Cheng, B., Sahasrabuddhe, K., Luo, Y. and Simons, J., “Microspring characterization and flip chip assembly reliability,” 42nd International Symposium on Microelectronics (IMAPS), San Jose, CA, Nov. 2009.Google Scholar
9 Zhu, Q., Ma, L. and Sitaraman, S. K., “β-Helix: A lithography-Based Compliant Off-Chip Interconnect,” IEEE Transactions on Components and Packaging Technologies, Vol.26, No.3 (2003), pp.582590.Google Scholar
10 Zhu, Q., Ma, L. and Sitaraman, S. K., “Design Optimization of One-Turn Helix: A Novel Compliant Off-chip Interconnect,” IEEE Transactions on Advanced Packaging, Vol.26, No.2 (2002), pp.106112.Google Scholar
11 Bakir, M. S, Reed, H.A., Thacker, H.D., Patel, C.S., Kohl, P.A., Martin, K.P., and Meindl, J.D, “Sea of Leads (SoL) Ultrahigh Density Wafer-Level Chip Input/Output Interconnections for Gigascale Integration (GSI),” IEEE Transactions on Electron Devices, vol.50, no.10 (2003) pp.20392048.Google Scholar
12 Basavanhally, N. et al, “High-Density Solder Bump Interconnect for MEMS Hybrid Integration,” Advanced Packaging, IEEE Transactions on, Vol. 30, 2007, pp. 622628.Google Scholar
13 Mitchell, J. et al., “Integrating Novel Packaging Technologies for Large Scale Computer Systems,” Proc. Of InterPACK, July 2009.Google Scholar
14 Shubin, I. et al. “Novel packaging with rematable spring interconnect chips for MCM,” 59th Electronic Components and Technology Conference, San Diego, CA, USA: 2009, pp. 10531058.Google Scholar
15 Yang, H. S., Ravindran, R., Bakir, M.S. and Meindl, J.D., “A 3D Interconnect System for Large Biosensor Array and CMOS Signal-Processing IC Integration,” Proc. of IEEE International Interconnect Technology Conference, Burlingame, CA, June 2010.Google Scholar
16 Ravindran, R., Sadie, J. A., Scarberry, K. E., Yang, H. S., Bakir, M. S., McDonald, J. F., and Meindl, J. D., “Biochemical Sensing with an Arrayed Silicon Nanowire Platform,” Proc. IEEE 60th Electronic Components and Technology Conference, June 2010 Google Scholar
17 Leung, L. and Chen, K., “Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, 2005, pp. 24722480.Google Scholar
18 Lai, J., Yang, H. S., Chen, H., King, C., Zaveri, J., Ravindran, R. and Bakir, M. S., “A ‘mesh’ seed layer for improved through-silicon-via fabrication,” Journal of Micromechanics and Microengineering, Vol. 20, No. 2 (2010).Google Scholar