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Investigation of Mechanical Stresses in Underlying Silicon due to Lead-Tin Solder Bumps via Synchrotron X-Ray Topography and Finite Element Analysis

Published online by Cambridge University Press:  21 March 2011

J. Kanatharana ,
J.J. Pérez-Camacho ,
T. Buckley ,
P.J. McNally ,
T. Tuomi ,
A.N. Danilewsky ,
M. O'Hare ,
D. Lowney  and
W. Chen
J. Kanatharana
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
J.J. Pérez-Camacho
Affiliation:
Materials and Failure Analysis Group, Intel Ireland Fab Operations, Leixlip, Co.Kildare, Ireland
T. Buckley
Affiliation:
Materials and Failure Analysis Group, Intel Ireland Fab Operations, Leixlip, Co.Kildare, Ireland
P.J. McNally
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
T. Tuomi
Affiliation:
Optoelectronics Laboratory, Helsinki University of Technology, 02015 TKK, Finland
A.N. Danilewsky
Affiliation:
D-79108, Freiburg, Germany
M. O'Hare
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
D. Lowney
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
W. Chen
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
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Abstract

Solder based flip-chip packaging has prompted interest in many integrated circuit (IC)packaging applications due to its many advantages in terms of cost, package size, electricalperformance, input/output density, etc. The ball grid array (BGA) is one of the most commonflip-chip packaging techniques used for microprocessor applications. However, mechanicalstresses induced by the flip-chip process can impact adversely on the reliability of production.

White beam synchrotron x-ray topography (SXRT), a non-destructive technique, has beenemployed to investigate the spatial extent of strain fields imposed on the underlying siliconsubstrate for Intelν®Pentiumν®III microprocessors due to the lead-tin solder bump process for BGApackaging. Large area and section back-reflection SXRT images were taken before and after asimulation of the reflow process at 350°C in atmosphere. The presence of induced strain fields inthe Si substrate due to the overlying bump structures has been observed via the extinction contrasteffect in these x-ray topographs. In addition, orientational contrast effects have also been foundafter the reflow process due to the severe stresses in the underlying silicon beneath the lead bumps.The estimated magnitudes of stress, ∣σ∣, imposed on the underlying silicon were calculated to be100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the leadbumps were removed from the wafer, which confirms that the bumps are indeed a major source ofstrain in the underlying Si. Finite element analysis (FEA) has also been performed in 2-D planestrain mode. The magnitudes and spatial distribution of the stresses after the reflow process are ingood agreement with the SXRT results.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 682: Symposium N – Microelectronics and Microsystems Packaging , 2001 , N5.7
Copyright
Copyright © Materials Research Society 2001

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