Hostname: page-component-cd9895bd7-p9bg8 Total loading time: 0 Render date: 2024-12-28T06:58:48.367Z Has data issue: false hasContentIssue false
  • English
  • Français

Investigation of Mechanical Stresses in Underlying Silicon due to Lead-Tin Solder Bumps via Synchrotron X-Ray Topography and Finite Element Analysis

Published online by Cambridge University Press:  21 March 2011

J. Kanatharana ,
J.J. Pérez-Camacho ,
T. Buckley ,
P.J. McNally ,
T. Tuomi ,
A.N. Danilewsky ,
M. O'Hare ,
D. Lowney  and
W. Chen
J. Kanatharana
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
J.J. Pérez-Camacho
Affiliation:
Materials and Failure Analysis Group, Intel Ireland Fab Operations, Leixlip, Co.Kildare, Ireland
T. Buckley
Affiliation:
Materials and Failure Analysis Group, Intel Ireland Fab Operations, Leixlip, Co.Kildare, Ireland
P.J. McNally
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
T. Tuomi
Affiliation:
Optoelectronics Laboratory, Helsinki University of Technology, 02015 TKK, Finland
A.N. Danilewsky
Affiliation:
D-79108, Freiburg, Germany
M. O'Hare
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
D. Lowney
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
W. Chen
Affiliation:
Research Institute for Network and Communications Engineering (RINCE), School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
Get access

Abstract

Solder based flip-chip packaging has prompted interest in many integrated circuit (IC)packaging applications due to its many advantages in terms of cost, package size, electricalperformance, input/output density, etc. The ball grid array (BGA) is one of the most commonflip-chip packaging techniques used for microprocessor applications. However, mechanicalstresses induced by the flip-chip process can impact adversely on the reliability of production.

White beam synchrotron x-ray topography (SXRT), a non-destructive technique, has beenemployed to investigate the spatial extent of strain fields imposed on the underlying siliconsubstrate for Intelν®Pentiumν®III microprocessors due to the lead-tin solder bump process for BGApackaging. Large area and section back-reflection SXRT images were taken before and after asimulation of the reflow process at 350°C in atmosphere. The presence of induced strain fields inthe Si substrate due to the overlying bump structures has been observed via the extinction contrasteffect in these x-ray topographs. In addition, orientational contrast effects have also been foundafter the reflow process due to the severe stresses in the underlying silicon beneath the lead bumps.The estimated magnitudes of stress, ∣σ∣, imposed on the underlying silicon were calculated to be100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the leadbumps were removed from the wafer, which confirms that the bumps are indeed a major source ofstrain in the underlying Si. Finite element analysis (FEA) has also been performed in 2-D planestrain mode. The magnitudes and spatial distribution of the stresses after the reflow process are ingood agreement with the SXRT results.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 682: Symposium N – Microelectronics and Microsystems Packaging , 2001 , N5.7
Copyright
Copyright © Materials Research Society 2001

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Blackwell, G.R., Chapter 4: Direct Chip Attach, The Electronic Packaging Handbook, ed. Blackwell, G.R.(CRC Press, 1999).Google Scholar
2. Nagesh, V.K., Peddada, R., Ramalingam, S., Sur, B. and Tai, A., Challenges of Flip Chip on Organic substrateAssembly Technology, IEEE Proceeding 1999 Electronics Component and technology conference, pp.975–978 (1999).Google Scholar
3. McNally, P.J., Curley, J., Bolt, M., Reader, A., Tuomi, T., Rantamaki, R., Danilewsky, A. and wolf, I. De, Monitoring of Stress Reduction in Shallow Trench Isolation CMOS structures Via Synchrotron X-rayTopography, Electrical Data and Raman Spectroscopy, Journal of Materials Science: Materials inElectronics 10, pp.351–358 (1999).Google Scholar
4. Wang, J., Qian, Z. and Liu, S., Process Induced Stresses of a Flip-Chip Packaging by Sequential ProcessingModeling Technique, Transactions of the ASME, Journal of Electronic Packaging 120, pp.309–313 (1998).Google Scholar
5. Yao, Q. and Qu, J., Three-Dimensional Versus Two-Dimensional Finite Element Modeling of Flip-ChipPackages, Transactions of the ASME, Journal of Electronic Packaging 121, pp.196–201 (1999).Google Scholar
6. Variyam, M.N., Xie, W. and Sitaraman, S.K., Role of Out-of-Plane Coefficient of Thermal Expansion inElectronic Packaging Modeling, Transactions of the ASME, Journal of Electronic Packaging 122, pp.121–127 (2000).Google Scholar
7. Tuomi, T., Naukkarinen, K. and Rabe, P., Use of Synchrotron Radiation in X-ray Diffraction Topography,Phys. Stat. Sol. A 25, pp.93–106 (1974).Google Scholar
8. McNally, P.J., Curley, J., Krier, A., Mao, Y., Richardson, J., Tuomi, T., Taskinen, M., Rantamaki, R., Prieurand, E. Danilewsky, A., An Evaluation of Liquid Phase Epitaxial InGaAs/InAs Heterostructures for InfraredDevices Using Synchrotron X-ray Topography, Semiconductor Science and Technology 13, pp.345–349(1998).Google Scholar
9. Rantamaki, R., X-ray Topography of Semiconductors using Synchrotron Radiation, HD. Sci Thesis, Optoelectronics Laboratory, Department of Electrical and Communications Engineering, HelsinkiUniversity of Technology, pp.11–12 (1999).Google Scholar
10. Brand, A., Haranahalli, A., Hsieh, N., Lin, Y.C., Sery, G., Stenton, N., Woo, B.J., Ahmed, S., Bohr, M., Yang, S., “Intel's 0.25 Micron, 2.0 Volts Logic Process Technology”, Intel Technology Journal, 3rd Quarter 1998.http://developer.intel.com/technology/itj/q31998Google Scholar
11. Meieran, E.S. and Blech, I.A., X-ray Extinction Contrast Topography of Silicon Strained by Thin SurfaceFilms, Journal of Applied Physics 36, pp.3162–3167 (1965).Google Scholar
12. Karilahti, M., Tuomi, T., Taskinen, M., Tulkki, J., Lipsanen, H. and McNally, P., Synchrotron X-rayTopographic Study of Strain in Silicon Wafers with Intergrated Circuits, IL Nuovo Cimento, 19D(2-4), pp.181–184 (1997).Google Scholar
13. King, J.A., Materials, Handbook for Hybrid Microelectronics (Artech, USA, 1988).Google Scholar
14. Quickfield™, www.quickfield.comGoogle Scholar